Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
article

Iterative schedule optimization for voltage scalable distributed embedded systems

Published: 01 February 2004 Publication History

Abstract

We present an iterative schedule optimization for multirate system specifications, mapped onto heterogeneous distributed architectures containing dynamic voltage scalable processing elements (DVS-PEs). To achieve a high degree of energy reduction, we formulate a generalized DVS problem, taking into account the power variations among the executing tasks. An efficient heuristic is presented that identifies optimized supply voltages by not only "simply" exploiting slack time, but under the additional consideration of the power profiles. Thereby, this algorithm minimizes the energy dissipation of heterogeneous architectures, including power-managed processing elements, effectively. Further, we address the simultaneous schedule optimization toward timing behavior and DVS utilization by integrating the proposed DVS heuristic into a genetic list scheduling approach. We investigate and analyze the possible energy reduction at both steps of the co-synthesis (voltage scaling and scheduling), including the power variations effects. Extensive experiments indicate that the presented work produces solutions with high quality.

References

[1]
Bambha, N., Bhattacharyya, S., Teich, J., and Zitzler, E. 2001. Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors. In Proceedings of the 1st International Symposium on Hardware/Software Co-Design (CODES'01), 243--248.]]
[2]
Brandolese, C., Fornaciari, W., Salice, F., and Sciuto, D. 2000. Energy estimation for 32 bit microprocessors. In Proceedings of the 8th International Workshop Hardware/Software Co-Design (CODES'00), 24--28.]]
[3]
Burd, T. D. 2001. Energy-efficient processor system design. Ph.D. thesis, University of California at Berkeley.]]
[4]
Burd, T. D. and Brodersen, R. W. 1996. Processor design for portable systems. J. VLSI Signal Processing 13, 2 (Aug.), 203--222.]]
[5]
Burd, T. D., Pering, T. A., Stratakos, A. J., and Brodersen, R. W. 2000. A dynamic voltage scaled microprocessor system. IEEE J. Solid-State Circuits 35, 11 (Nov.), 1571--1580.]]
[6]
Chretienne, P., Coffman, E. G., Lenstra, J. K., and Liu, Z. 1995. Scheduling Theory and its Applications. Wiley, New York.]]
[7]
Devadas, S. and Malik, S. 1995. A survey of optimization techniques targeting low power VLSI circuits. In Proceedings of the IEEE 32nd Design Automation Conference (DAC95), 242--247.]]
[8]
Dhodhi, M. K., Ahmad, I., and Storer, R. 1995. SHEMUS: Synthesis of heterogeneous multiprocessor systems. J. Microprocessors and Microsystems 19, 6 (Aug.), 311--319.]]
[9]
Dick, R., Rhodes, D., and Wolf, W. 1998. TGFF: Task graphs for free. In Proceedings of the 5th International Workshop on Hardware/Software Co-Design (Codes/CASHE'97), 97--101.]]
[10]
Dick, R. P. and Jha, N. K. 1998. MOGAC: A multiobjective genetic algorithm for hardware-software co-synthesis of distributed embedded systems. IEEE Trans. Computer-Aided Design 17, 10 (Oct.), 920--935.]]
[11]
Eles, P., Peng, Z., Kuchcinski, K., and Doboli, A. 1997. System level hardware/software partitioning based on simulated annealing and tabu search. J. Design Automation Embedded Systems 2, 5--32.]]
[12]
Ernst, R., Henkel, J., and Brenner, T. 1993. Hardware-software co-synthesis for mirco-controllers. IEEE Design & Test of Comp. 10, 4 (Dec.), 64--75.]]
[13]
Fogarty, T. C. 1989. Varying the probability of mutation in the genetic algorithm. In Proceedings of the 3rd International Conference on Genetic Algorithms (ICGA), 104--109.]]
[14]
Fornaciari, W., Sciuto, D., and Silvano, C. 1999. Power estimation for architectural exploration of HW/SW communication on system-level buses. In Proceedings of the 7th International Workshop on Hardware/Software Co-Design (CODES'99), 152--156.]]
[15]
Garey, M. R. and Johnson, D. S. 1979. Computers and Intractability: A Guide to the theory of NP-Completeness. W.H. Freeman and Company, San Francisco, CA.]]
[16]
Goldberg, D. E. 1989. Genetic Algorithms in Search, Optimization & Machine Learning. Addison-Wesley, San Mateo, CA.]]
[17]
Grajcar, M. 1999. Genetic list scheduling algorithm for scheduling and allocation on a loosely coupled heterogeneous multiprocessor system. In Proceedings of the IEEE 36th Design Automation Conference (DAC99), 280--285.]]
[18]
Gruian, F. 2000. System-level design methods for low-energy architectures containing variable voltage processors. In Workshop on Power-Aware Computing Systems.]]
[19]
Gruian, F. and Kuchcinski, K. 2001. LEneS: task scheduling for low-energy systems using variable supply voltage processors. In Proceedings of the Asia South Pacific-Design Automation Conference (ASP-DAC'01), 449--455.]]
[20]
Gutnik, V. and Chandrakasan, A. 1997. Embedded power supply for low-power DSP. IEEE Trans. VLSI Systems 5, 4, 425--435.]]
[21]
Henkel, J., Benner, T., and Ernst, R. 1993. Hardware generation and partitioning effects in the COSYMA system. In Proceedings of the International Workshop on Hardware/Software Co-Design (Codes/CASHE'93).]]
[22]
Henkel, J. and Ernst, R. 2001. An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques. IEEE Trans. VLSI Systems 9, 2, 273--289.]]
[23]
Hong, I., Kirovski, D., Qu, G., Potkonjak, M., and Srivastava, M. B. 1999. Power optimization of variable-voltage core-based systems. IEEE Trans. Computer-Aided Design 18, 12 (Dec.), 1702--1714.]]
[24]
Hou, J. and Wolf, W. 1996. Process partitioning for distributed embedded systems. In Proceedings of the CODES, 70--76.]]
[25]
Intel® XScaleRM. 2000. Developer's Manual. Order number 273473--001.]]
[26]
Ishihara, T. and Yasuura, H. 1998. Voltage scheduling problem for dynamically variable voltage processors. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'98), 197--202.]]
[27]
Kalavade, A. 1995. System-level codesign of mixed hardware-software systems. Ph.D. thesis, University of California, Berkeley.]]
[28]
Kirovski, D. and Potkonjak, M. 1997. System-level synthesis of low-power hard real-time systems. In Proceedings of the IEEE 34th Design Automation Conference (DAC97), 697--702.]]
[29]
Klaiber, A. 2000. The Technology behind crusoe processors. http://www.transmeta.com.]]
[30]
Lee, S. and Sakurai, T. 2000. Run-time voltage hopping for low-power real-time systems. In Proceedings of the IEEE 37th Design Automation Conference (DAC00), 806--809.]]
[31]
Li, Y.-T. S., Malik, S., and Wolfe, A. 1995. Performance estimation of embedded software with instruction cache modeling. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD-95), 380--387.]]
[32]
Liu, J., Chou, P. H., Bagherzadeh, N., and Kurdahi, F. 2001. Power-aware scheduling under timing constraints for mission-critical embedded systems. In Proceedings of the IEEE 38th Design Automation Conference (DAC01), 840--845.]]
[33]
Luo, J. and Jha, N. K. 2000. Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD-00), 357--364.]]
[34]
Luo, J. and Jha, N. K. 2001. Battery-aware static scheduling for distributed real-time embedded systems. In Proceedings of the IEEE 38th Design Automation Conference (DAC01), 444--449.]]
[35]
Manzak, A. and Chakrabarti, C. 2000. Variable voltage task scheduling for minimizing energy or minimizing power. In Proceedings of the International Conference on Acoustics, Speech, and Signal Processing (ICASSP00), 3239--3242.]]
[36]
Micheli, G. D. and Gupta, R. K. 1997. Hardware/software co-design. In Proceedings of the IEEE, 349--365.]]
[37]
Mobile AMD AthlonTM4. 2000. Processor model 6 CPGA data sheet. Publication no 24319 Rev E.]]
[38]
Muresan, R. and Gebotys, C. H. 2001. Current consumption dynamics at instruction and program level for a VLIW DSP processor. In Proceedings of the International Symposium on System Synthesis (ISSS'01), 130--135.]]
[39]
Okuma, T., Ishihara, T., and Yasuura, H. 1999. Real-time task scheduling for a variable voltage processor. In Proceedings of the International Symposium on System Synthesis (ISSS'99), 24--29.]]
[40]
Okuma, T., Ishihara, T., and Yasuura, H. 2001. Software energy reduction techniques for variable-voltage processors. IEEE Design & Test of Comp. 18, 2 (Mar.--Apr.), 31--41.]]
[41]
Pedram, M. 1996. Power minimization in IC design: principles and applications. ACM Trans. Design Automation of Electronic Systems 1, 1 (Jan.), 3--56.]]
[42]
Pering, T., Burd, T. D., and Brodersen, R. B. 1998. The simulation and evaluation for dynamic voltage scaling algorithms. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED'98), 76--81.]]
[43]
Prakash, S. and Parker, A. 1992. SOS: Synthesis of application-specific heterogeneous multiprocessor systems. J. Parallel & Distributed Computing, 338--351.]]
[44]
Quan, G. and Hu, X. S. 2001. Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors. In Proceedings of the IEEE 38th Design Automation Conference (DAC01), 828--833.]]
[45]
Quan, G. and Hu, X. S. 2002. Minimum energy fixed-priority scheduling for variable voltage processors. In Proceedings of the Design, Automation and Test in Europe Conference (DATE2002), 782--787.]]
[46]
Rogers, A. and Prügel-Bennett, A. 1999. Modelling the dynamics of a steady-state genetic algorithm. In Foundations of Genetic Algorithms (FOGA-5). 57--68.]]
[47]
Schmitz, M. T. 2003. Energy minimization techniques for distributed embedded systems. Ph.D. thesis, University of Southampton.]]
[48]
Schmitz, M. T. and Al-Hashimi, B. M. 2001. Considering power variations of DVS processing elements for energy minimization in distributed systems. In Proceedings of the International Symposium on System Synthesis (ISSS'01), 250--255.]]
[49]
Schmitz, M. T., Al-Hashimi, B. M., and Eles, P. 2002. Energy-efficient mapping and scheduling for DVS enabled distributed embedded systems. In Proceedings of the Design, Automation and Test in Europe Conference (DATE2002), 514--521.]]
[50]
Shin, Y. and Choi, K. 1999. Power conscious fixed priority scheduling for hard real-time systems. In Proceedings of the IEEE 36th Design Automation Conference (DAC99), 134--139.]]
[51]
Shin, Y., Choi, K., and Sakurai, T. 2000. Power optimization of real-time embedded systems on variable speed processors. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD-00), 365--368.]]
[52]
Sih, G. C. and Lee, E. A. 1993. A compile-time scheduling heuristic for interconnection-constrained heterogeneous processor architectures. IEEE Trans. Parallel and Distributed Systems 4, 2 (Feb.), 175--187.]]
[53]
Simunic, T., Benini, L., Acquaviva, A., Glynn, P., and Micheli, G. D. 2001. Dynamic voltage scaling and power management for portable systems. In Proceedings of the IEEE 38th Design Automation Conference (DAC01), 524--529.]]
[54]
Teich, J., Blickle, T., and Thiele, L. 1997. An evolutionary approach to system-level synthesis. In Proceedings of the 5th International Workshop on Hardware/Software Co-Design (Codes/CASHE'97), 167--171.]]
[55]
Tiwari, V., Malik, S., and Wolfe, A. 1994. Power analysis of embedded software: A first step towards software power minimization. IEEE Trans. VLSI Systems.]]
[56]
Weiser, M., Welch, B., Demers, A., and Shenker, S. 1994. Scheduling for reduced CPU energy. In Proceedings of the USENIX Symposium on Operating Systems Design and Implementation (OSDI), 13--23.]]
[57]
WITAS. The Wallenberg Laboratory for research on information technology and autonomous system. http://www.ida.liu.se/ext/witas/.]]
[58]
Wolf, W. H. 1994. Hardware/software co-design of embedded systems. In Proceedings of the IEEE, 967--989.]]
[59]
Wolf, W. H. 1997. An architectural co-synthesis algorithm for distributed, embedded computing systems. IEEE Trans. VLSI Systems 5, 2 (June), 218--229.]]
[60]
Wu, M. and Gajski, D. 1990. Hypertool: A programming aid for message-passing systems. IEEE Trans. Parallel and Distributed Systems 1, 3 (July), 330--343.]]
[61]
Xie, Y. and Wolf, W. 2001. Allocation and scheduling of conditional task graph in hardware/software co-synthesis. In Proceedings of the Design, Automation and Test in Europe Conference (DATE2001), 620--625.]]
[62]
Zhang, Y., Hu, X., and Chen, D. Z. 2002. Task scheduling and voltage selection for energy minimization. In Proceedings of the IEEE 39th Design Automation Conference (DAC02), 183--188.]]

Cited By

View all
  • (2022)A Survey on Energy-Aware Scheduling using Genetic Algorithms2022 2nd International Conference on Intelligent Cybernetics Technology & Applications (ICICyTA)10.1109/ICICyTA57421.2022.10038154(59-64)Online publication date: 15-Dec-2022
  • (2019)Energy-Efficient Scheduling of Tasks with Conditional Precedence Constraints on MPSoCsTowards Integrated Web, Mobile, and IoT Technology10.1007/978-3-030-28430-5_6(115-145)Online publication date: 10-Aug-2019
  • (2017)A hybrid Big Bang-Big Crunch algorithm for energy optimization on heterogeneous distributed systemMATEC Web of Conferences10.1051/matecconf/201711901047119(01047)Online publication date: 4-Aug-2017
  • Show More Cited By

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 3, Issue 1
February 2004
232 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/972627
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

Publication History

Published: 01 February 2004
Published in TECS Volume 3, Issue 1

Permissions

Request permissions for this article.

Check for updates

Author Tags

  1. Dynamic voltage scaling
  2. embedded systems
  3. energy minimization
  4. heterogeneous distributed systems
  5. scheduling
  6. system synthesis

Qualifiers

  • Article

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)4
  • Downloads (Last 6 weeks)0
Reflects downloads up to 13 Nov 2024

Other Metrics

Citations

Cited By

View all
  • (2022)A Survey on Energy-Aware Scheduling using Genetic Algorithms2022 2nd International Conference on Intelligent Cybernetics Technology & Applications (ICICyTA)10.1109/ICICyTA57421.2022.10038154(59-64)Online publication date: 15-Dec-2022
  • (2019)Energy-Efficient Scheduling of Tasks with Conditional Precedence Constraints on MPSoCsTowards Integrated Web, Mobile, and IoT Technology10.1007/978-3-030-28430-5_6(115-145)Online publication date: 10-Aug-2019
  • (2017)A hybrid Big Bang-Big Crunch algorithm for energy optimization on heterogeneous distributed systemMATEC Web of Conferences10.1051/matecconf/201711901047119(01047)Online publication date: 4-Aug-2017
  • (2016)Energy-Aware Task Scheduling with Precedence and Deadline Constraints on MPSoCs2016 IEEE 18th International Conference on High Performance Computing and Communications; IEEE 14th International Conference on Smart City; IEEE 2nd International Conference on Data Science and Systems (HPCC/SmartCity/DSS)10.1109/HPCC-SmartCity-DSS.2016.0163(1163-1172)Online publication date: Dec-2016
  • (2016)Worst-Case Finish Time Analysis for DAG-Based Applications in the Presence of Transient FaultsJournal of Computer Science and Technology10.1007/s11390-016-1626-631:2(267-283)Online publication date: 7-Mar-2016
  • (2014)An Improved Estimation of Distribution Algorithm for Dynamic Voltage Scaling Problem in Heterogeneous SystemApplied Mechanics and Materials10.4028/www.scientific.net/AMM.631-632.373631-632(373-377)Online publication date: Sep-2014
  • (2013)Framework for simulation of heterogeneous MpSoC for design space explorationVLSI Design10.1155/2013/9361812013(11-11)Online publication date: 1-Jan-2013
  • (2013)Literature SurveyModeling, Analysis and Optimization of Network-on-Chip Communication Architectures10.1007/978-94-007-3958-1_2(9-32)Online publication date: 13-Mar-2013
  • (2013)An Ant Colony System for Dynamic Voltage Scaling Problem in Heterogeneous SystemComputer Engineering and Networking10.1007/978-3-319-01766-2_9(73-81)Online publication date: 5-Dec-2013
  • (2012)Networks on chips: structure and design methodologiesJournal of Electrical and Computer Engineering10.1155/2012/5094652012(2-2)Online publication date: 1-Jan-2012
  • Show More Cited By

View Options

Get Access

Login options

Full Access

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media