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A Practical Approach for Bus Architecture Optimization at Transaction Level

Published: 03 March 2003 Publication History

Abstract

For multimedia applications, the System LSI design trend is to integrate an increasing number of applications running on a single chip. Traditional architectures have reached their limit in terms of performance. New architectures must be explored to fulfill the system application needs. Complex bus structures have been introduced. These bus architectures open a much larger exploration space than traditional hardware-software partitioning trade-offs. We have been researching methods to leverage these new architectural elements. We also introduce a design environment to apply practical and efficient methods in todayýs design flow. Two key technologies are supporting our method and environment: Automatic bus architecture synthesis for easy configuration of bus architecture and transaction level of abstraction for communication for improvement of simulation performance. In this paper, we show the design method, an overview of the design environment and its usefulness through experimental results.

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Cited By

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  • (2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
  • (2011)EPIDETOXProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039433(381-384)Online publication date: 9-Oct-2011
  • (2010)TLM automation for multi-core designProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899888(717-724)Online publication date: 18-Jan-2010
  • Show More Cited By

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cover image ACM Conferences
DATE '03: Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
March 2003
292 pages
ISBN:0769518702

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IEEE Computer Society

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Published: 03 March 2003

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
  • (2011)EPIDETOXProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039433(381-384)Online publication date: 9-Oct-2011
  • (2010)TLM automation for multi-core designProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899888(717-724)Online publication date: 18-Jan-2010
  • (2009)Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal modelProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509764(558-563)Online publication date: 19-Jan-2009
  • (2008)Fast exploration of bus-based communication architectures at the CCATB abstractionACM Transactions on Embedded Computing Systems10.1145/1331331.13313467:2(1-32)Online publication date: 29-Jan-2008
  • (2006)COSMECAProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131680(700-705)Online publication date: 6-Mar-2006
  • (2006)A systematic IP and bus subsystem modeling for platform-based system designProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131639(560-564)Online publication date: 6-Mar-2006
  • (2006)Exploiting TLM and object introspection for system-level simulationProceedings of the conference on Design, automation and test in Europe: Proceedings10.5555/1131481.1131515(100-105)Online publication date: 6-Mar-2006
  • (2006)Constraint-driven bus matrix synthesis for MPSoCProceedings of the 2006 Asia and South Pacific Design Automation Conference10.1145/1118299.1118309(30-35)Online publication date: 24-Jan-2006
  • (2005)A Network Traffic Generator Model for Fast Network-on-Chip SimulationProceedings of the conference on Design, Automation and Test in Europe - Volume 210.1109/DATE.2005.22(780-785)Online publication date: 7-Mar-2005
  • Show More Cited By

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