research-article

Automatic generation of Cycle Accurate and Cycle Count Accurate transaction level bus models from a formal model

Authors:

Ren Song TsayAuthors Info & Claims

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

Pages 558 - 563

Published: 19 January 2009 Publication History

Abstract

This paper proposes the first automatic approach to simultaneously generate Cycle Accurate and Cycle Count Accurate transaction level bus models. Since TLM (Transaction Level Modeling) is proven as an effective design methodology for managing the ever-increasing complexity of system level designs, researchers often exploit various abstraction levels to gain either simulation speed or accuracy. Consequently, designers repeatedly perform the time-consuming task of re-writing and performing consistency checks for different abstraction level models of the same design. To ease the work, we propose a correct-by-construction method that automatically and simultaneously generates both fast and accurate transaction level bus models for system simulation. The proposed approach relieves designers from the tedious and error-prone process of refining models and checking for consistency.

References

[1]

T. Grötker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer Academic Publishers, 2002.

Digital Library

[2]

D. Gajski, J. Zhu, R. Domer, A. Gerstlaner, and S. Zhao, SpecC: Specification Language and Methodology, Kluwer Academic Publishers, 2000.

[3]

S. Malik, X. Zhu, "A hierarchical modeling framework for on-chip communication architectures", Proc. Computer-Aided Design, 2002, pp. 663--671.

Digital Library

[4]

O. Ogawa, et al., "A practical approach for bus architecture optimization at transaction level", Design, Automation and Test in Europe Conf., 2003, pp. 176--181.

Digital Library

[5]

M. Caldari, et al., "Transaction-level models for AMBA bus architecture using SystemC 2.0", Design, Automation and Test in Europe Conf., 2003, pp. 26--31.

Digital Library

[6]

A. Harverinen, M. Leclercq, N. Weyrich, D. Wingard, "A SystemC#8482; OCP Transaction Level Communication Channel", Technical Report'07.

[7]

W. Klingauf, R. Günzel, O. Bringmann, P. Parfuntseu, and M. Burton, "GreenBus: a generic interconnect fabric for transaction level modeling", Proc. Design Automation Conf., 2006, pp. 905--910.

Digital Library

[8]

S. Pasricha, N. Dutt, M. Ben-Romdhane, "Extending the Transaction Level Modeling Approach for Fast Communication Architecture Exploration", Proc. Design Automation Conf., 2004, pp. 113--118.

Digital Library

[9]

Open SystemC Initiative (OSCI). SystemC Version 2 Documentation. http://www.systemc.org.

[10]

D. Shin, A. Gerstlauer, J. Peng, R. Dömer, and D. Gajski, "Automatic generation of transaction level models for rapid design space exploration," Proc. Hardware/Software Codesign and System Synthesis, 2006, pp. 64--69.

Digital Library

[11]

S. Vercauteren, B. Lin, and H. D. Man, "Constructing Application-Specific Heterogeneous Embedded Architectures from Custom HW/SW Applications," Proc. Design Automation Conf., June 1996, pp. 521--526.

Digital Library

[12]

Jon. D. Kleinsmith and D. Gajski, "Communication Synthesis for Reuse", UC Irvine, ICS-TR-98-06, March 1998.

[13]

T. Michiels, "Generating TLM bus models from formal protocol specifications", European SystemC Users Group Meeting, 2004.

[14]

V. D'silva, S. Ramesh, and A. Sowmya, "Synchronous Protocol Automata: A Framework for Modeling and Verification of SoC Communication Architectures", Proc. Design, Automation and Test in Europe, 2004, pp. 20--27.

Digital Library

[15]

Open Core Protocol International Partnership (OCP-IP), www.ocpip.org.

[16]

D. Flynn. "AMBA: enabling reusable on-chip designs", IEEE Micro, 1997, pp. 20--27.

Digital Library

Cited By

Chen SChen CTsay RFettweis GNebel W(2014)An activity-sensitive contention delay model for highly efficient deterministic full-system simulationsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616868(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616868
Lo CLi MChen LLu YTsay RHuang HYeh J(2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems (TECS)10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
https://dl.acm.org/doi/10.1145/2536747.2536759
Boncalo ODobre AAmaricai ATanase ARiley GQuaglia FHimmelspach J(2012)A cycle-count-accurate simulation platform with enhanced design exploration capabilityProceedings of the 5th International ICST Conference on Simulation Tools and Techniques10.5555/2263019.2263033(113-118)Online publication date: 19-Mar-2012
https://dl.acm.org/doi/10.5555/2263019.2263033
Show More Cited By

Recommendations

Automatic generation of bus functional models from transaction level models
ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

This paper presents methodology and algorithms for generating bus functional models from transaction level models in system level design. Transaction level models are often used by designers for prototyping the bus functional architecture of the system. ...
Cycle-Accurate Network on Chip Simulation with Noxim

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance,...
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
Special Section on ESTIMedia'10

Although pipelined/out-of-order (PL/OO) execution features are commonly supported by the state-of-the-art bus designs, no existing manual Transaction-Level-Modeling (TLM) approaches can effectively construct fast and accurate simulation models for PL/OO ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASP-DAC '09: Proceedings of the 2009 Asia and South Pacific Design Automation Conference

January 2009

902 pages

ISBN:9781424427482

General Chair:
Kazutoshi Wakabayashi
NEC Corporation

Sponsors

IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IPSJ SIGSLDM: Information Processing Society of Japan - SIG System LSI Design Methodology
IEICE ESS: Institute of Electronics, Information and Communication Engineers - Engineering Sciences Society

Publisher

IEEE Press

Publication History

Published: 19 January 2009

Check for updates

Qualifiers

Research-article

Conference

ASPDAC '09

Sponsor:

SIGDA
IPSJ SIGSLDM
IEICE ESS

ASPDAC '09: Asia and South Pacific Design Automation Conference

January 19 - 22, 2009

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

5
Total Citations
View Citations
153
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Chen SChen CTsay RFettweis GNebel W(2014)An activity-sensitive contention delay model for highly efficient deterministic full-system simulationsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616868(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616868
Lo CLi MChen LLu YTsay RHuang HYeh J(2013)Automatic generation of high-speed accurate TLM models for out-of-order pipelined busACM Transactions on Embedded Computing Systems (TECS)10.1145/2536747.253675913:1s(1-25)Online publication date: 6-Dec-2013
https://dl.acm.org/doi/10.1145/2536747.2536759
Boncalo ODobre AAmaricai ATanase ARiley GQuaglia FHimmelspach J(2012)A cycle-count-accurate simulation platform with enhanced design exploration capabilityProceedings of the 5th International ICST Conference on Simulation Tools and Techniques10.5555/2263019.2263033(113-118)Online publication date: 19-Mar-2012
https://dl.acm.org/doi/10.5555/2263019.2263033
Huang YLu YWu HTsay RGroeneveld PSciuto DHassoun S(2012)A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulationProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228384(127-132)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228384
Lo YLi MTsay RRosenstiel WWakabayashi K(2009)Cycle count accurate memory modeling in system level designProceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1629435.1629475(287-294)Online publication date: 11-Oct-2009
https://dl.acm.org/doi/10.1145/1629435.1629475

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents