A cycle-count-accurate simulation platform with enhanced design exploration capability
Pages 113 - 118
Abstract
This paper presents a simulation platform for architecture exploration of bus based heterogeneous multi-processor system-on chips (MPSoC) -- moviSim. The tradeoff between accurate simulation results and simulation time has been obtained by the cycle-count-accurate approach. Its main attributes are: flexibility, integration with the targeted tool chain and increased tracing and analysis capability. The wide range of implemented metrics (program execution time, executed instructions, stalled cycles, bus logging, register and memory port detection, power consumption, function, data and code line profiling, cache metrics (miss/hit ratio, etc), number of memory/subsystem reads/writes performed by a master) allow enhanced architectural exploration capability for complex MPSoC on which large software applications are running. Due to easy integration with debugging tools, the source code targeting the hardware platform can be easily verified and analyzed with the proposed simulation platform.
References
[1]
Chen-Kang Lo, Li-Chun Chen, Meng-Huan Wu, and Ren-Song Tsay. Cycle-Count-Accurate Processor Modeling for Fast and Accurate System-Level Simulation. in Proc. of Design, Automation & Test in Europe Conference, 2011
[2]
Zhe-Mao Hsu, Jen-Chieh Yeh, and I-Yao Chuang. An Accurate System Architecture Refinement Methodology with Mixed Abstraction-Level Virtual Platform. in Proc. of Design, Automation & Test in Europe Conference, 2010
[3]
Gabor Madl, Sudeep Pasricha, Qiang Zhu, Luis Angel D. Bathen, Nikil Dutt, Formal Performance Evaluation of AMBA-based System-on-Chip Designs. in Proc. of EMSOFT, 2006
[4]
OSCI. SystemC ver 2.1 (IEEE 1666 Standard), 2005.
[5]
Y. Lo, M. Li, and R. Tsay, Cycle count accurate memory modeling in system level design, in Proc. of the conf. on Hardware/Software Codesign and System Synthesis, 2009
[6]
S. Pasricha, N. Dutt, and M. Ben-Romdhane, Extending the Transaction Level Modeling Approach for Fast Communication Architectures Exploration, in Proc. of the Design Automation Conf., pp. 113--118, 2004
[7]
C. K. Lo and R. S. Tsay. Automatic Generation of Cycle Accurate and Cycle Count Accurate Transaction Level Bus Models from a Formal Model, in Proc. of ASPDAC, 2009
[8]
AMBA AXI Specification www.arm.com/armtech/AXI
[9]
M. Dales -- SWARM Simulator -- http://www.cl.cam.ac.uk/~mwd24/phd/swarm.html, 2003
[10]
G. Mouchard -- MicroLib PowerPC750 Simulator -- http://www.lri.fr/~mouchard/PowerPC750/, 2002
[11]
Hiren D. Patel and Sandeep K. Shukla. Model-Driven Validation of SystemC Designs, Hindawi Publishing CorporationEURASIP Journal on Embedded Systems, 2008.
[12]
Cong J., Gururaj K., Han G., Kaplan A., Naik M., Reinman G. MC-Sim: An Efficient Simulation Tool for MPSoC Design. In Proceeding of the IEEE/SCM Conference on Computer-Aided Design (ICCAD), 364--371, 2008
[13]
Makela J. M., Paakkuleinen J., Leppanen V. MVTSim -- Software Simulator for Multicore on Chip Parallel Architectures. In Proceedings International Conference on Computer Systems and Technologies -- CompSysTech, Article No. 15, 2009
[14]
Renau J., Fraguela B., Tuck J., Liu W., Prvulovic M., Ceze L., Sarangi S., Sack P., Strauss K., Montesinos P. SESC Simulator, Available at: http://sesc.sourceforge.net, 2005
[15]
International Telecommunication Union. Advanced Video Coding for Generic Audiovisual Services. - H264 Standard, 2005
[16]
A. Amaricai, A. Dobre, O. Boncalo, A. Tanase, C. Valuch. Models and Implementations of Hardware Interface Modules in a Multi-Processor System-on-Chip Simulator. in Proc. of the conf. 6th IEEE SACI, 2011
Index Terms
- A cycle-count-accurate simulation platform with enhanced design exploration capability
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Published In
March 2012
402 pages
ISBN:9781450315104
- General Chair:
- George Riley,
- Program Chairs:
- Francesco Quaglia,
- Jan Himmelspach
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Publisher
ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)
Brussels, Belgium
Publication History
Published: 19 March 2012
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SIMUTOOLS'12
SIMUTOOLS'12: International ICST Conference on Simulation Tools and Techniques
March 19 - 23, 2012
Desenzano del Garda, Italy
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Overall Acceptance Rate 20 of 73 submissions, 27%
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