article

Input data reuse in compiling window operations onto reconfigurable hardware

Authors:

Betul Buyukkurt,

Walid NajjarAuthors Info & Claims

ACM SIGPLAN Notices, Volume 39, Issue 7

Pages 249 - 256

https://doi.org/10.1145/998300.997199

Published: 11 June 2004 Publication History

Abstract

Balancing computation with I/O has been considered as a critical factor of the overall performance for embedded systems in general and reconfigurable computing systems in particular. Data I/O often dominates the overall computation performance for window operation, which are frequently used in image processing, image compression, pattern recognition and digital signal processing. This problem is more acute in reconfigurable systems since the compiler must generate the data path and the sequence of operations. The challenge is to intelligently exploit data reuse on the reconfigurable fabric (FPGA) to minimize the required memory or I/O bandwidth while maximizing parallelism.In this paper, we present a compile-time approach to reuse data in window-based codes. The compiler, called ROCCC, first analyzes and optimizes the window operation in C. It then computes the size of the hardware buffer and defines three sets of data values for each window: the window set, the managed set and the killed set. This compile-time analysis simplifies the HDL code generation and improves the resulting hardware performance. We also discuss in-place window operations.

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Cited By

Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch2
Choudhury ZShrivastava SRamapantulu LPurini S(2022)An FPGA Overlay for CNN Inference with Fine-grained Flexible ParallelismACM Transactions on Architecture and Code Optimization10.1145/351959819:3(1-26)Online publication date: 4-May-2022
https://dl.acm.org/doi/10.1145/3519598
Sousa ÉHannig FTeich J(2018)Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable ArraysSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_18(218-229)Online publication date: 17-Apr-2018
https://doi.org/10.1007/978-3-319-90023-0_18
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Index Terms

Input data reuse in compiling window operations onto reconfigurable hardware

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Input data reuse in compiling window operations onto reconfigurable hardware
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Published In

cover image ACM SIGPLAN Notices

ACM SIGPLAN Notices Volume 39, Issue 7

LCTES '04

July 2004

265 pages

ISSN:0362-1340

EISSN:1558-1160

DOI:10.1145/998300

Issue’s Table of Contents

LCTES '04: Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
June 2004
276 pages
ISBN:1581138067
DOI:10.1145/997163
General Chair:
David Whalley
Florida State University
,
Program Chair:
Ron Cytron
Washington University

Copyright © 2004 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 11 June 2004

Published in SIGPLAN Volume 39, Issue 7

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Cited By

Bailey D(2023)Field‐programmable Gate ArraysDesign for Embedded Image Processing on FPGAs10.1002/9781119819820.ch2(19-44)Online publication date: 5-Sep-2023
https://doi.org/10.1002/9781119819820.ch2
Choudhury ZShrivastava SRamapantulu LPurini S(2022)An FPGA Overlay for CNN Inference with Fine-grained Flexible ParallelismACM Transactions on Architecture and Code Optimization10.1145/351959819:3(1-26)Online publication date: 4-May-2022
https://dl.acm.org/doi/10.1145/3519598
Sousa ÉHannig FTeich J(2018)Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable ArraysSystem Level Design from HW/SW to Memory for Embedded Systems10.1007/978-3-319-90023-0_18(218-229)Online publication date: 17-Apr-2018
https://doi.org/10.1007/978-3-319-90023-0_18
Zhang CLiang TMok PYu W(2017)FPGA Implementation of the Coupled Filtering Method and the Affine Warping MethodIEEE Transactions on NanoBioscience10.1109/TNB.2017.270510416:5(314-325)Online publication date: Jul-2017
https://doi.org/10.1109/TNB.2017.2705104
Najjar WVillarreal JHalstead R(2016)ROCCC 2.0FPGAs for Software Programmers10.1007/978-3-319-26408-0_11(191-204)Online publication date: 18-Jun-2016
https://doi.org/10.1007/978-3-319-26408-0_11
Bailey DCarmona-Galán RRodríguez-Vázquez Á(2015)The advantages and limitations of high level synthesis for FPGA based image processingProceedings of the 9th International Conference on Distributed Smart Cameras10.1145/2789116.2789145(134-139)Online publication date: 8-Sep-2015
https://dl.acm.org/doi/10.1145/2789116.2789145
Aubertin PLanglois JSavaria Y(2012)Real-time computation of local neighborhood functions in application-specific instruction-set processorsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2011.217020420:11(2031-2043)Online publication date: 1-Nov-2012
https://dl.acm.org/doi/10.1109/TVLSI.2011.2170204
Cardoso JDiniz PWeinhardt M(2010)Compiling for reconfigurable computingACM Computing Surveys10.1145/1749603.174960442:4(1-65)Online publication date: 23-Jun-2010
https://dl.acm.org/doi/10.1145/1749603.1749604
Vahid F(2009)What is hardware/software partitioning?ACM SIGDA Newsletter10.1145/1862900.186290139:6(1-1)Online publication date: 1-Jun-2009
https://dl.acm.org/doi/10.1145/1862900.1862901
Hagiescu AWong WBacon DRabbah R(2009)A computing origamiProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629987(282-287)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629987
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