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High-Level Language Abstraction for Reconfigurable Computing

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Charles RossAuthors Info & Claims

Computer, Volume 36, Issue 8

Pages 63 - 69

https://doi.org/10.1109/MC.2003.1220583

Published: 01 August 2003 Publication History

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Abstract

Reconfigurable computing systems typically consist of an array of configurable computing elements. The computational granularity of these elements ranges from simple gates to complete arithmetic logic units, with or without registers. A rich programmable interconnect completes the array.Performance evaluation of Simple-Assignment C, a high-level, algorithmic language for one-step compilation to host code and field-programmable-gate-array configuration codes, has just begun, with the authors porting the system to a more complex board that contains three FPGAs.

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Sudvarg MZhao CHtet YKonst MLang TSong NChamberlain RBuhler JBuckley J(2024)HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne InstrumentProceedings of the 21st ACM International Conference on Computing Frontiers10.1145/3649153.3649209(115-125)Online publication date: 7-May-2024
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High-Level Language Abstraction for Reconfigurable Computing
1. Hardware

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Published In

Computer Volume 36, Issue 8

August 2003

90 pages

ISSN:0018-9162

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 August 2003

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Sudvarg MZhao CHtet YKonst MLang TSong NChamberlain RBuhler JBuckley J(2024)HLS Taking Flight: Toward Using High-Level Synthesis Techniques in a Space-Borne InstrumentProceedings of the 21st ACM International Conference on Computing Frontiers10.1145/3649153.3649209(115-125)Online publication date: 7-May-2024
https://dl.acm.org/doi/10.1145/3649153.3649209
Choudhury ZGulati APurini S(2023)FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific CompilerACM Transactions on Architecture and Code Optimization10.1145/362952320:4(1-25)Online publication date: 25-Oct-2023
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Majumder KBondhugula UAamodt TSwift MJerger N(2023)HIR: An MLIR-based Intermediate Representation for Hardware Accelerator DescriptionProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 410.1145/3623278.3624767(189-201)Online publication date: 25-Mar-2023
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Huang LLi DWang KGao TTavares A(2020)A Survey on Performance Optimization of High-Level Synthesis ToolsJournal of Computer Science and Technology10.1007/s11390-020-9414-835:3(697-720)Online publication date: 1-May-2020
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Abid MJerbi KRaulet MDéforges OAbid M(2018)Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFOJournal of Signal Processing Systems10.1007/s11265-017-1226-x90:1(127-144)Online publication date: 1-Jan-2018
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Chugh NVasista VPurini SBondhugula UZaks AMendelson BRauchwerger LHwu W(2016)A DSL Compiler for Accelerating Image Processing Pipelines on FPGAsProceedings of the 2016 International Conference on Parallel Architectures and Compilation10.1145/2967938.2967969(327-338)Online publication date: 11-Sep-2016
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Sérot JBerry FBourrasset C(2016)High-level dataflow programming for real-time image processing on smart camerasJournal of Real-Time Image Processing10.1007/s11554-014-0462-612:4(635-647)Online publication date: 1-Dec-2016
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Fowers JLiu JStitt GCorporaal HStuijk S(2014)A framework for dynamic parallelization of FPGA-accelerated applicationsProceedings of the 17th International Workshop on Software and Compilers for Embedded Systems10.1145/2609248.2609256(1-10)Online publication date: 10-Jun-2014
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