article

JIST: Just-In-Time scheduling translation for parallel processors

Authors:

Giovanni Agosta,

Stefano Crespi Reghizzi,

Gerlando Falauto,

Martino SykoraAuthors Info & Claims

Scientific Programming, Volume 13, Issue 3

Pages 239 - 253

https://doi.org/10.1155/2005/127158

Published: 01 July 2005 Publication History

Abstract

The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures.

We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

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Cited By

Rokicki SRohou EDerrien S(2019)Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIWIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286428838:10(1872-1885)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2864288
Rokicki SRohou EDerrien S(2017)Hardware-accelerated dynamic binary translationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130632(1062-1067)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130632

JIST: Just-In-Time scheduling translation for parallel processors
1. Software and its engineering
  1. Software notations and tools
    1. General programming languages

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cover image Scientific Programming

Scientific Programming Volume 13, Issue 3

July 2005

74 pages

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IOS Press

Netherlands

Publication History

Published: 01 July 2005

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Cited By

Rokicki SRohou EDerrien S(2019)Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIWIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.286428838:10(1872-1885)Online publication date: 17-Sep-2019
https://dl.acm.org/doi/10.1109/TCAD.2018.2864288
Rokicki SRohou EDerrien S(2017)Hardware-accelerated dynamic binary translationProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130632(1062-1067)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130632

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