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Hardware-accelerated dynamic binary translation

Published: 27 March 2017 Publication History

Abstract

Dynamic Binary Translation (DBT) is often used in hardware/software co-design to take advantage of an architecture model while using binaries from another one. The co-development of the DBT engine and of the execution architecture leads to architecture with special support to these mechanisms. In this work, we propose a hardware accelerated Dynamic Binary Translation where the first steps of the DBT process are fully accelerated in hardware. Results shows that using our hardware accelerators leads to a speed-up of 8× and a cost in energy 18× lower, compared with an equivalent software approach.

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Cited By

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  • (2019)TranskernelProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358865(675-691)Online publication date: 10-Jul-2019
  • (2019)A retargetable system-level DBT hypervisorProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358850(505-520)Online publication date: 10-Jul-2019
  1. Hardware-accelerated dynamic binary translation

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    Published In

    cover image Guide Proceedings
    DATE '17: Proceedings of the Conference on Design, Automation & Test in Europe
    March 2017
    1814 pages

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    European Design and Automation Association

    Leuven, Belgium

    Publication History

    Published: 27 March 2017

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    • (2019)TranskernelProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358865(675-691)Online publication date: 10-Jul-2019
    • (2019)A retargetable system-level DBT hypervisorProceedings of the 2019 USENIX Conference on Usenix Annual Technical Conference10.5555/3358807.3358850(505-520)Online publication date: 10-Jul-2019

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