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A high-efficiency monolithic DC-DC PFM boost converter with parallel power MOS technique

Published: 01 January 2013 Publication History

Abstract

This paper presents a high-efficiency monolithic dc-dc PFM boost converter designed with a standard TSMC3.3/5V 0.35 µm CMOS technology. The proposed boost converter combines the parallel power MOS technique with pulse-frequency modulation (PFM) technique to achieve high efficiency over a wide load current range, extending battery life and reducing the cost for the portable systems. The proposed parallel power MOS controller and load current detector exactly determine the size of power MOS to increase power conversion efficiency in different loads. Postlayout simulation results of the designed circuit show that the power conversion is 74.9-90.7% efficiency over a load range from 1mA to 420mA with 1.5V supply. Moreover, the proposed boost converter has a smaller area and lower cost than those of the existing boost converter circuits.

References

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  1. A high-efficiency monolithic DC-DC PFM boost converter with parallel power MOS technique

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    Published In

    cover image VLSI Design
    VLSI Design  Volume 2013, Issue
    Special issue on Advanced VLSI Design Methodologies for Emerging Industrial Multimedia and Communication Applications
    January 2013
    47 pages
    ISSN:1065-514X
    EISSN:1563-5171
    Issue’s Table of Contents

    Publisher

    Hindawi Limited

    London, United Kingdom

    Publication History

    Accepted: 12 April 2013
    Published: 01 January 2013
    Received: 26 December 2012

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