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View all- Chu TYu SHwang C(2017)Corrigendum to “High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability”VLSI Design10.1155/2017/68989162017Online publication date: 1-Jan-2017
High-accuracy programmable timing generator with wide-range tuning capability
Abstract
In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18 µm 1P6M technology. The test chip area occupies 1.9mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14 ps resolution with the clock rate at 550MHz. The INL and DNL are within -0.21 ∼ +0.78 and -0.27 ∼ +0.43 LSB, respectively.
References
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J. Chapman, J. Currin, and S. Payne, "A low-cost highperformance CMOS timing vernier for ATE," in Proceedings of the International Test Conference, pp. 459-468, Washington, DC, USA, October 1995.
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Hindawi Limited
London, United Kingdom
Publication History
Accepted: 01 April 2013
Published: 01 January 2013
Received: 27 December 2012
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View all- Chu TYu SHwang C(2017)Corrigendum to “High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability”VLSI Design10.1155/2017/68989162017Online publication date: 1-Jan-2017
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