A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC
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Abstract
This paper presents a framework for high-level exploration, Register Transfer-Level RTL design and rapid prototyping of Network-on-Chip NoC architectures. From the high-level exploration, a selected NoC topology is derived, which is then implemented in RTL using an automated design flow. Furthermore, for verification purposes, appropriate self-checking testbenches for the verification of the RTL and architecture files for the semi-automatic implementation of the system in Xilinx EDK are also generated, significantly reducing design and verification time, and therefore Non-Recurring Engineering NRE cost. Simulation and FPGA implementation results are given for four case studies multimedia applications, proving the validity of the proposed approach.
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Published: 01 July 2013
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