The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networks-on-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future systems like virtualization, power, thermal and application management, as well as new challenges in technology scaling like reliability and variability. The introduction of networks-on-chip into the platform enables a component-oriented architectural design which is out of reach of current design methods. This paper presents an overview of the achievements at the end of the second out of three years of planned activities.

References

[1]

S. Rodrigo, S. Medardoni, J. Flich, D. Bertozzi, and J. Duato. Efficient implementation of distributed routing algorithms for NoCs. IET Computers and Digital Techniques, 3:460--475, 2009.

Crossref

Google Scholar

[2]

F. O. Sem-Jacobsen, S. Rodrigo Mocholi, A. Strano, T. Skeie, D. Bertozzi, and F. Gilabert. Enabling power efficiency through dynamic rerouting on-chip. ACM TECS Special Issue on On-Chip and Off-Chip Network Architectures, 2011.

Google Scholar

[3]

T. Skeie, F. O. Sem-Jacobsen, S. Rodrigo Mocholi, J. Flich, D. Bertozzi, and S. Medardoni. Flexible dor routing for virtualization of multicore chips. In International Symposium on System-on-Chip, 2009.

Digital Library

Google Scholar

[4]

A. Strano, C. G. Requena, D. Ludovici, M. E. Gomez, and M. Favalli. Exploiting network-on-chip structural redundancy for a cooperative and scalable built-in self-test architecture. In Proceedings of DATE, 2011.

Crossref

Google Scholar

[5]

X. Wang, M. Yang, Y. Jiang, and P. Liu. On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks. Microprocessors and Microsystems, 35(2):119--129, Mar. 2011.

Digital Library

Google Scholar

[6]

F.-C. Yang, Y.-T. Lin, S. Kundu, C.-F. Kao, and I.-J. Huang. An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS VOL. 19 NO. 4, March 2011.

Digital Library

Google Scholar

[7]

H. Yi, S. Park, and S. Kundu. A Design-for-Debug (DfD) for NoC-based SoC Debugging via NoC. 17th Asian Test Symposium, 2008.

Digital Library

Google Scholar

[8]

J. Zhang, M. Yan, and S. Li. Debug Support for Scalable System-on-Chip. Seventh International Workshop on Microprocessor Test and Verification, 2006.

Digital Library

Google Scholar

Cited By

View all

Tatas KSiozios KBartzas AKyriacou CSoudris D(2013)A Novel Prototyping and Evaluation Framework for NoC-Based MPSoCInternational Journal of Adaptive, Resilient and Autonomic Systems10.4018/jaras.20130701014:3(1-24)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.4018/jaras.2013070101
Tatas KSiozios KSoudris DJantsch ATatas KSiozios KSoudris DJantsch A(2013)The SYSMANTIC NoC Design and Prototyping FrameworkDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_10(237-255)Online publication date: 9-Oct-2013
https://doi.org/10.1007/978-1-4614-4274-5_10

Index Terms

Quest for the ultimate network-on-chip: the NaNoC project
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

Cycle-Accurate Network on Chip Simulation with Noxim

The on-chip communication in current Chip-MultiProcessors (CMP) and MultiProcessor-SoC (MPSoC) is mainly based on the Network-on-Chip (NoC) design paradigm. Unfortunately, it is foreseen that conventional NoC architectures cannot sustain the performance,...
3D network-on-chip design for embedded ubiquitous computing systems

A novel 3D NoC topology for embedded ubiquitous computing is proposed.A minimal routing algorithm with path diversity in the 3D NoC Topology is used.A power efficient architecture design for NoC-based embedded ubiquitous computing is introduced. ...
Leveraging dark silicon to optimize networks-on-chip topology

This paper presents a reconfigurable network-on-chip (NoC) for many-core chip multiprocessors (CMPs) in the dark silicon era, where a considerable part of high-end chips cannot be powered up due to the power and bandwidth walls. Core specialization, ...

Comments

Information & Contributors

Information

Published In

INA-OCMC '12: Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop

January 2012

51 pages

ISBN:9781450310109

DOI:10.1145/2107763

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 25 January 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

INA-OCMC '12

INA-OCMC '12: On-Chip, Multi-Chip

January 25, 2012

Paris, France

Acceptance Rates

Overall Acceptance Rate 12 of 27 submissions, 44%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

2
Total Citations
View Citations
255
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)0

Reflects downloads up to 13 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Tatas KSiozios KBartzas AKyriacou CSoudris D(2013)A Novel Prototyping and Evaluation Framework for NoC-Based MPSoCInternational Journal of Adaptive, Resilient and Autonomic Systems10.4018/jaras.20130701014:3(1-24)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.4018/jaras.2013070101
Tatas KSiozios KSoudris DJantsch ATatas KSiozios KSoudris DJantsch A(2013)The SYSMANTIC NoC Design and Prototyping FrameworkDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_10(237-255)Online publication date: 9-Oct-2013
https://doi.org/10.1007/978-1-4614-4274-5_10

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Cycle-Accurate Network on Chip Simulation with Noxim

3D network-on-chip design for embedded ubiquitous computing systems

Leveraging dark silicon to optimize networks-on-chip topology

Comments

Published In

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Other Metrics

Article Metrics

Other Metrics

Cited By

Login options

Full Access

PDF

eReader

Abstract

References

Cited By

Index Terms

Recommendations

Cycle-Accurate Network on Chip Simulation with Noxim

3D network-on-chip design for embedded ubiquitous computing systems

Leveraging dark silicon to optimize networks-on-chip topology

Comments

Information

Published In

Publisher

Publication History

Permissions

Check for updates

Author Tags

Qualifiers

Conference

Acceptance Rates

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

Get Access

Login options

Full Access

View options

PDF

eReader

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations