The NaNoC project is progressing toward an innovative design platform for multicore systems based on future networks-on-chip. This platform enables the design, manufacturing and management of networks-on-chip by tackling new requirements of future systems like virtualization, power, thermal and application management, as well as new challenges in technology scaling like reliability and variability. The introduction of networks-on-chip into the platform enables a component-oriented architectural design which is out of reach of current design methods. This paper presents an overview of the achievements at the end of the second out of three years of planned activities.

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Tatas KSiozios KBartzas AKyriacou CSoudris D(2013)A Novel Prototyping and Evaluation Framework for NoC-Based MPSoCInternational Journal of Adaptive, Resilient and Autonomic Systems10.4018/jaras.20130701014:3(1-24)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.4018/jaras.2013070101
Tatas KSiozios KSoudris DJantsch ATatas KSiozios KSoudris DJantsch A(2013)The SYSMANTIC NoC Design and Prototyping FrameworkDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_10(237-255)Online publication date: 9-Oct-2013
https://doi.org/10.1007/978-1-4614-4274-5_10

Index Terms

Quest for the ultimate network-on-chip: the NaNoC project
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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INA-OCMC '12: Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop

January 2012

51 pages

ISBN:9781450310109

DOI:10.1145/2107763

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Published: 25 January 2012

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Tatas KSiozios KBartzas AKyriacou CSoudris D(2013)A Novel Prototyping and Evaluation Framework for NoC-Based MPSoCInternational Journal of Adaptive, Resilient and Autonomic Systems10.4018/jaras.20130701014:3(1-24)Online publication date: 1-Jul-2013
https://dl.acm.org/doi/10.4018/jaras.2013070101
Tatas KSiozios KSoudris DJantsch ATatas KSiozios KSoudris DJantsch A(2013)The SYSMANTIC NoC Design and Prototyping FrameworkDesigning 2D and 3D Network-on-Chip Architectures10.1007/978-1-4614-4274-5_10(237-255)Online publication date: 9-Oct-2013
https://doi.org/10.1007/978-1-4614-4274-5_10

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3D network-on-chip design for embedded ubiquitous computing systems

Leveraging dark silicon to optimize networks-on-chip topology

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Cycle-Accurate Network on Chip Simulation with Noxim

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