Article

Using positive equality to prove liveness for pipelined microprocessors

Author:

Miroslav N. VelevAuthors Info & Claims

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Pages 316 - 321

Published: 27 January 2004 Publication History

Abstract

The paper presents an indirect method to automatically prove liveness for pipelined microprocessors. This is done by first proving safety---correctness for one step, starting from an arbitrary initial state that is possibly restricted by invariant constraints. By induction, the implementation will be correct for any number of steps; we need to prove that for some fixed number of steps, n, the implementation will fetch at least one instruction that will be completed. This was proved efficiently by using the property of Positive Equality. Modeling restrictions made the method applicable to designs with exceptions and branch prediction. The indirect method and the modeling restrictions resulted in 4 orders of magnitude speedup, enabling the automatic liveness proof for dual-issue superscalar and VLIW designs.

References

[1]

M. D. Aagaard, N. A. Day, and M. Lou, "Relating multi-step and single-step microprocessor correctness statements," Formal Methods in Computer-Aided Design (FMCAD '02), M. D. Aagaard, and J. W. O'Leary, eds., LNCS 2517, Springer-Verlag, November 2002, pp. 123--141.]]

Digital Library

[2]

M. D. Aagaard, B. Cook, N. A. Day, and R. B. Jones, "A framework for superscalar microprocessor correctness statements," Software Tools for Technology Transfer (STTT), Vol. 4, No. 3 (May 2003), pp. 298--312.]]

[3]

A. Biere, C. Artho, and V. Schuppan, "Liveness checking as safety checking," Electronic Notes in Theoretical Computer Science 66, 2002.]]

[4]

R. E. Bryant, S. German, and M. N. Velev, "Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic," ACM Transactions on Computational Logic (TOCL), Vol. 2, No. 1 (January 2001), pp. 93--134.]]

Digital Library

[5]

R. E. Bryant, and M. N. Velev, "Boolean satisfiability with transitivity constraints," ACM Transactions on Computational Logic (TOCL), Vol. 3, No. 4 (October 2002), pp. 604--627.]]

Digital Library

[6]

J. R. Burch, and D. L. Dill, "Automated verification of pipelined microprocessor control," Computer-Aided Verification (CAV '94), D. L. Dill, ed., LNCS 818, Springer-Verlag, June 1994, pp. 68--80.]]

Digital Library

[7]

J. R. Burch, "Techniques for verifying superscalar microprocessors," 33rd Design Automation Conference (DAC '96), June 1996.]]

Digital Library

[8]

A. Goel, K. Sajid, H. Zhou, A. Aziz, and V. Singhal, "BDD based procedures for a theory of equality with uninterpreted functions," Computer-Aided Verification (CAV '98), A. J. Hu, and M. Y. Vardi, eds., LNCS 1427, Springer-Verlag, June 1998, pp. 244--255.]]

Digital Library

[9]

J. L. Hennessy, and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3rd edition, Morgan Kaufmann, San Francisco, 2002.]]

Digital Library

[10]

T. A. Henzinger, S. Qadeer, and S. K. Rajamani, "Decomposing refinement proofs using assume-guarantee reasoning," International Conference on Computer-Aided Design (ICCAD '00), November 2000, pp. 245--252.]]

Digital Library

[11]

R. Hosabettu, M. Srivas, and G. Gopalakrishnan, "Proof of correctness of a processor with reorder buffer using the completion functions approach," Computer-Aided Verification (CAV '99), LNCS 1633, Springer-Verlag, 1999.]]

Digital Library

[12]

C. Jacobi, and D. Kröning, "Proving the correctness of a complete microprocessor," 30. Jahrestagung der Gesellshaft fur Informatik, Springer-Verlag, 2000.]]

[13]

D. Kröning, and W. J. Paul, "Automated pipeline design," 38th Design Automation Conference (DAC '01), June 2001, pp. 810--815.]]

Digital Library

[14]

S. Lahiri, C. Pixley, and K. Albin, "Experience with term level modeling and verification of the M. CORE#8482; microprocessor core," International Workshop on High Level Design, Validation and Test (HLDVT '01), November 2001.]]

Digital Library

[15]

S. K. Lahiri, S. A. Seshia, and R. E. Bryant, "Modeling and verification of out-of-order microprocessors in UCLID," Formal Methods in Computer-Aided Design (FMCAD '02), LNCS 2517, Springer-Verlag, November 2002.]]

Digital Library

[16]

L. Lamport, "Proving the correctness of multiprocess programs," IEEE Transactions on Software Engineering," Vol. 3, No. 2 (March 1977), pp. 125--143.]]

Digital Library

[17]

D. Le Berre, and L. Simon, "Results from the SAT'03 solver competion," 6th International Conference on Theory and Applications of Satisfiability Testing (SAT '03), 2003. http://www.lri.fr/~simon/contest03/results/]]

[18]

P. Manolios, "Mechanical verification of reactive systems," Ph.D. Thesis, Department of Computer Sciences, University of Texas at Austin, 2001.]]

[19]

K. L. McMillan, "Circular compositional reasoning about liveness," Technical Report, Cadence Berkeley Labs, 1999.]]

[20]

S. M. Müller, and W. J. Paul, Computer Architecture: Complexity and Correctness, Springer-Verlag, 2000.]]

Digital Library

[21]

A. Pnueli, J. Xu, and L. Zuck, "Liveness with (0, 1, infinity)-counter abstraction," Computer-Aided Verification, (CAV '02), E. Brinksma, and K. G. Larsen, eds., LNCS 2404, Springer-Verlag, July 2002, pp. 107--122.]]

Digital Library

[22]

A. Pnueli, Y. Rodeh, O. Strichman, and M. Siegel, "The small model property: how small can it be?", Journal of Information and Computation, Vol. 178, No. 1 (October 2002), pp. 279--293.]]

Digital Library

[23]

L. Ryan, Siege SAT Solver v.3. http://www.cs.sfu.ca/~loryan/personal/]]

[24]

J. Sawada, "Verification of a simple pipelined machine model," in Computer-Aided Reasoning: ACL2 Case Studies, Kluwer Academic Publishers, Boston/Dordrecht/London, 2000.]]

Digital Library

[25]

H. Sharangpani, and K. Arora, "Itanium processor microarchitecture," IEEE Micro, Vol. 20, No. 5 (September-October 2000), pp. 24--43.]]

Digital Library

[26]

M. K. Srivas, and S. P. Miller, "Formal verification of an avionics microprocessor," Technical Report CSL-95-4, SRI International, 1995.]]

Digital Library

[27]

M. N. Velev, and R. E. Bryant, "Exploiting positive equality and partial non-consistency in the formal verification of pipelined microprocessors," 36th Design Automation Conference (DAC '99), June 1999, pp. 397--401.]]

Digital Library

[28]

M. N. Velev, and R. E. Bryant, "Superscalar processor verification using efficient reductions of the logic of equality with uninterpreted functions to propositional logic," Correct Hardware Design and Verification Methods (CHARME '99), LNCS 1703, Springer-Verlag, September 1999, pp. 37--53.]]

Digital Library

[29]

M. N. Velev, and R. E. Bryant, "Formal verification of superscalar microprocessors with multicycle functional units, exceptions, and branch prediction," 37th Design Automation Conference (DAC '00), June 2000, pp. 112--117.]]

Digital Library

[30]

M. N. Velev, "Formal verification of VLIW microprocessors with speculative execution," Computer-Aided Verification (CAV '00), E. A. Emerson, and A. P. Sistla, eds., LNCS 1855, Springer-Verlag, July 2000, pp. 296--311.]]

Digital Library

[31]

M. N. Velev, "Automatic abstraction of memories in the formal verification of superscalar microprocessors," Tools and Algorithms for the Construction and Analysis of Systems (TACAS '01), T. Margaria, and W. Yi, eds., LNCS 2031, Springer-Verlag, April 2001, pp. 252--267.]]

Digital Library

[32]

M. N. Velev, and R. E. Bryant, "EVC: a validity checker for the logic of equality with uninterpreted functions and memories, exploiting positive equality and conservative transformations," Computer-Aided Verification (CAV '01), LNCS 2102, Springer-Verlag, July 2001, pp. 235--240.]]

Digital Library

[33]

M. N. Velev, and R. E. Bryant, "Effective use of boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors," Journal of Symbolic Computation (JSC), Vol. 35, No. 2 (February 2003), pp. 73--106.]]

Digital Library

[34]

M. N. Velev, "Integrating formal verification into an advanced computer architecture course," ASEE Annual Conference & Exposition, June 2003.]]

[35]

M. N. Velev, "Automatic abstraction of equations in a logic of equality," Automated Reasoning with Analytic Tableaux and Related Methods (TABLEAUX '03), M. C. Mayer, and F. Pirri, eds., LNAI 2796, Springer-Verlag, September 2003, pp. 196--213.]]

[36]

M. N. Velev, "Collection of high-level microprocessor bugs from formal verification of pipelined and superscalar designs," International Test Conference (ITC '03), October 2003, pp. 138--147.]]

Cited By

Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
Velev MGao P(2011)Automatic formal verification of reconfigurable DSPsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950881(293-296)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950881
Show More Cited By

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Information

Published In

cover image ACM Conferences

ASP-DAC '04: Proceedings of the 2004 Asia and South Pacific Design Automation Conference

January 2004

957 pages

ISBN:0780381750

General Chair:
Masaharu Imai
Osaka University

Sponsors

IPSJ: Information Processing Society of Japan
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE: Institute of Electronics, Information and Communication Engineers

Publisher

IEEE Press

Publication History

Published: 27 January 2004

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ASPDAC04

Sponsor:

IPSJ
SIGDA
IEICE

ASPDAC04: Asia and South Pacific Design Automation Conference 2004

January 27 - 30, 2004

Yokohama, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

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ASPDAC '25

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sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

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Cited By

Velev MGao PPhillips JHu AGraeb H(2011)Automatic formal verification of multithreaded pipelined microprocessorsProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132476(679-686)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132476
Velev MGao P(2011)Exploiting abstraction for efficient formal verification of DSPs with arrays of reconfigurable functional unitsProceedings of the 13th international conference on Formal methods and software engineering10.5555/2075089.2075117(307-322)Online publication date: 26-Oct-2011
https://dl.acm.org/doi/10.5555/2075089.2075117
Velev MGao P(2011)Automatic formal verification of reconfigurable DSPsProceedings of the 16th Asia and South Pacific Design Automation Conference10.5555/1950815.1950881(293-296)Online publication date: 25-Jan-2011
https://dl.acm.org/doi/10.5555/1950815.1950881
Velev MGao P(2010)Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessorsProceedings of the 12th international conference on Formal engineering methods and software engineering10.5555/1939864.1939894(355-370)Online publication date: 17-Nov-2010
https://dl.acm.org/doi/10.5555/1939864.1939894
Velev MGao PLin Y(2010)A method for debugging of pipelined processors in formal verification by correspondence checkingProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899866(619-624)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899866
Manolios PSrinivasan S(2008)Automatic verification of safety and liveness for pipelined machines using WEB refinementACM Transactions on Design Automation of Electronic Systems10.1145/1367045.136705413:3(1-19)Online publication date: 25-Jul-2008
https://dl.acm.org/doi/10.1145/1367045.1367054
Velev M(2005)Automatic formal verification of liveness for pipelined processors with multicycle functional unitsProceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods10.1007/11560548_10(97-113)Online publication date: 3-Oct-2005
https://dl.acm.org/doi/10.1007/11560548_10

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