article

Using Transport Triggered Architectures for Embedded Processor Design

Authors:

Henk Corporaal,

Marnix ArnoldAuthors Info & Claims

Integrated Computer-Aided Engineering, Volume 5, Issue 1

Pages 19 - 38

Published: 01 January 1998 Publication History

Abstract

In this paper we propose the usage of Transport Triggered Architectures (TTAs) as a template for the design of application specific processors. TTAs can be compared to VLIWs (Very Long Instruction Word processors); both exploit the instruction level parallelism available at compile-time. However, TTAs are programmed differently. TTAs combine a set of interesting features; apart from being fully programmable, they have favorable scaling characteristics, they easily incorporate arbitrary functionality, and their organization is well structured, allowing easy and automatic design. The paper explains these features. Based on this template a set of design tools has been developed; they include a parallelizing C/C++ compiler which exploits the available processor and application concurrency, aprocessor generator, simulators, profilers, and a tool for architecture exploration; these tools are integrated within a graphical user interface. In the paper we briefly describe these tools and demonstrate how they can be applied to a particular application. This example application is taken from the image processing area. It will be shown how the tools assist in exploring many solutions, including those which incorporate application specific functionality.

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Kultala HViitanen TBerg HJääskeläinen PMultanen JKokkonen MRaiskila KZetterman TTakala J(2019)LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio CoprocessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289750827:5(1029-1042)Online publication date: 24-Apr-2019
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Davis BBaird RGavin PSjälander MFinlayson IRasapour FCook GUh GWhalley DTyson GIyer RGarg S(2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
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Baird RGavin PSjälander MWhalley DUh G(2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureACM SIGPLAN Notices10.1145/2808704.275495250:5(1-10)Online publication date: 4-Jun-2015
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cover image Integrated Computer-Aided Engineering

Integrated Computer-Aided Engineering Volume 5, Issue 1

January 1998

91 pages

ISSN:1069-2509

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IOS Press

Netherlands

Publication History

Published: 01 January 1998

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Kultala HViitanen TBerg HJääskeläinen PMultanen JKokkonen MRaiskila KZetterman TTakala J(2019)LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio CoprocessorIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.289750827:5(1029-1042)Online publication date: 24-Apr-2019
https://dl.acm.org/doi/10.1109/TVLSI.2019.2897508
Davis BBaird RGavin PSjälander MFinlayson IRasapour FCook GUh GWhalley DTyson GIyer RGarg S(2015)Scheduling instruction effects for a statically pipelined processorProceedings of the 2015 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.5555/2830689.2830710(167-176)Online publication date: 4-Oct-2015
https://dl.acm.org/doi/10.5555/2830689.2830710
Baird RGavin PSjälander MWhalley DUh G(2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureACM SIGPLAN Notices10.1145/2808704.275495250:5(1-10)Online publication date: 4-Jun-2015
https://dl.acm.org/doi/10.1145/2808704.2754952
Baird RGavin PSjälander MWhalley DUh GNoh SFischmeister SXue J(2015)Optimizing Transfers of Control in the Static Pipeline ArchitectureProceedings of the 16th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems 2015 CD-ROM10.1145/2670529.2754952(1-10)Online publication date: 4-Jun-2015
https://dl.acm.org/doi/10.1145/2670529.2754952
Finlayson IDavis BGavin PUh GWhalley DSjälander MTyson G(2013)Improving processor efficiency by statically pipelining instructionsACM SIGPLAN Notices10.1145/2499369.246555948:5(33-44)Online publication date: 20-Jun-2013
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Finlayson IDavis BGavin PUh GWhalley DSjälander MTyson GFranke BXue J(2013)Improving processor efficiency by statically pipelining instructionsProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2491899.2465559(33-44)Online publication date: 20-Jun-2013
https://dl.acm.org/doi/10.1145/2491899.2465559
Finlayson IDavis BGavin PUh GWhalley DSjälander MTyson GFranke BXue J(2013)Improving processor efficiency by statically pipelining instructionsProceedings of the 14th ACM SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems10.1145/2465554.2465559(33-44)Online publication date: 20-Jun-2013
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Li YWang ZRuan JDai K(2007)A low-power globally synchronous locally asynchronous FFT processorProceedings of the Third international conference on High Performance Computing and Communications10.5555/2401945.2401971(168-179)Online publication date: 26-Sep-2007
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Wang MWu GWang Z(2007)Instruction selection for subword level parallelism optimizations for application specific instruction processorsProceedings of the 5th international conference on Parallel and Distributed Processing and Applications10.5555/2395970.2396061(946-957)Online publication date: 29-Aug-2007
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Li YWang ZZhao XRuan JDai K(2007)Design of a low-power embedded processor architecture using asynchronous function unitsProceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture10.5555/2392163.2392196(354-363)Online publication date: 23-Aug-2007
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