research-article

Bringing NoCs to 65 nm

Authors:

Antonio Pullini,

Federico Angiolini,

Srinivasan Murali,

Giovanni De Micheli,

Luca BeniniAuthors Info & Claims

IEEE Micro, Volume 27, Issue 5

Pages 75 - 85

Published: 01 September 2007 Publication History

Abstract

Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The authors present experimental results from fully working 65-nm NoC designs and a detailed scalability analysis.

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Cited By

(2018)Power-aware high level evaluation model of interconnect length of on-chip memory network topologyInternational Journal of Computational Science and Engineering10.5555/3292834.329284117:4(422-431)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.5555/3292834.3292841
Werner SNavaridas JLuján M(2016)A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-ChipACM Computing Surveys10.1145/288678148:4(1-36)Online publication date: 18-Mar-2016
https://dl.acm.org/doi/10.1145/2886781
Bokhari HJavaid HShafique MHenkel JParameswaran S(2014)darkNoCProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593117(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593117
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Bringing NoCs to 65 nm

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Information

Published In

cover image IEEE Micro

IEEE Micro Volume 27, Issue 5

September 2007

109 pages

ISSN:0272-1732

Issue’s Table of Contents

Copyright © 2007.

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 September 2007

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Cited By

(2018)Power-aware high level evaluation model of interconnect length of on-chip memory network topologyInternational Journal of Computational Science and Engineering10.5555/3292834.329284117:4(422-431)Online publication date: 1-Jan-2018
https://dl.acm.org/doi/10.5555/3292834.3292841
Werner SNavaridas JLuján M(2016)A Survey on Design Approaches to Circumvent Permanent Faults in Networks-on-ChipACM Computing Surveys10.1145/288678148:4(1-36)Online publication date: 18-Mar-2016
https://dl.acm.org/doi/10.1145/2886781
Bokhari HJavaid HShafique MHenkel JParameswaran S(2014)darkNoCProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593117(1-6)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1145/2593069.2593117
Manevich RPolishuk LCidon IKolodny A(2014)Designing single-cycle long links in hierarchical NoCsMicroprocessors & Microsystems10.1016/j.micpro.2014.05.00538:8(814-825)Online publication date: 1-Nov-2014
https://dl.acm.org/doi/10.1016/j.micpro.2014.05.005
Bakhoda AKim JAamodt T(2013)Designing on-chip networks for throughput acceleratorsACM Transactions on Architecture and Code Optimization10.1145/251242910:3(1-35)Online publication date: 16-Sep-2013
https://dl.acm.org/doi/10.1145/2512429
Abellán JFernández JAcacio MBertozzi DBortolotti DMarongiu ABenini LRosenstiel WMacii E(2012)Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCsProceedings of the Conference on Design, Automation and Test in Europe10.5555/2492708.2492831(491-496)Online publication date: 12-Mar-2012
https://dl.acm.org/doi/10.5555/2492708.2492831
Pellegrini AGreathouse JBertacco VLu STorrellas J(2012)ViperProceedings of the 39th Annual International Symposium on Computer Architecture10.5555/2337159.2337199(344-355)Online publication date: 9-Jun-2012
https://dl.acm.org/doi/10.5555/2337159.2337199
Pellegrini AGreathouse JBertacco V(2012)ViperACM SIGARCH Computer Architecture News10.1145/2366231.233719940:3(344-355)Online publication date: 9-Jun-2012
https://dl.acm.org/doi/10.1145/2366231.2337199
Chen CPark SKrishna TPeh LPhillips JHu AGraeb H(2011)A low-swing crossbar and link generator for low-power networks-on-chipProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132495(779-786)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132495
English TPopovici EMarculescu RKishinevsky MGinosar RChatha K(2011)Interconnect physical analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for cryptographic acceleratorsProceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip10.1145/1999946.1999982(225-232)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1999946.1999982
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