research-article

aelite: a flit-synchronous network on chip with composable and predictable services

Authors:

Andreas Hansson,

Mahesh Subburaman,

Kees GoossensAuthors Info & Claims

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 250 - 255

Published: 20 April 2009 Publication History

Abstract

To accommodate the growing number of applications integrated on a single chip, Networks on Chip (NoC) must offer scalability not only on the architectural, but also on the physical and functional level. In addition, real-time applications require Guaranteed Services (GS), with latency and throughput bounds. Traditionally, NoC architectures only deliver scalability on two of the aforementioned three levels, or do not offer GS.

In this paper we present the composable and predictable aelite NoC architecture, that offers only GS, based on flit-synchronous Time Division Multiplexing (TDM). In contrast to other TDM-based NoCs, scalability on the physical level is achieved by using mesochronous or asynchronous links. Functional scalability is accomplished by completely isolating applications, and by having a router architecture that does not limit the number of service levels or connections. We demonstrate how aelite delivers the requested service to hundreds of simultaneous connections, and does so with 5 times less area compared to a state-of-the-art NoC.

References

[1]

M. Rutten et al., "Dynamic reconfiguration of streaming graphs on a heterogeneous multiprocessor architecture," IS&T/SPIE Electron. Imag., vol. 5683, 2005.

[2]

A. Jantsch, "Models of computation for networks on chip," in Proc. ACSD, 2006.

Digital Library

[3]

T. Bjerregaard and J. Sparsø, "A scheduling discipline for latency and bandwidth guarantees in asynchronous network-on-chip," in Proc. ASYNC, 2005.

Digital Library

[4]

I. Miro Panades et al., "A low cost network-on-chip with guaranteed service well suited to the gals approach," in Proc. NANONET, 2006.

[5]

T. Bjerregaard et al., "A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method," in Proc. DATE, 2007.

Digital Library

[6]

D. Rostislav et al., "An asynchronous router for multiple service levels networks on chip," in Proc. ASYNC, 2005.

Digital Library

[7]

E. Beigne et al., "An asynchronous NOC architecture providing low latency service and its multi-level design framework," in Proc. ASYNC, 2005.

Digital Library

[8]

K. Goossens et al., "The Æthereal network on chip: Concepts, architectures, and implementations," IEEE Des. and Test of Comp., vol. 22, no. 5, 2005.

Digital Library

[9]

M. Millberg et al., "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proc. DATE, 2004.

Digital Library

[10]

J. Muttersbach et al., "Practical design of globally-asynchronous locally-synchronous systems," in Proc. ASYNC, 2000.

Digital Library

[11]

S. Stergiou et al., "Xpipes lite: A synthesis oriented design library for networks on chips," in Proc. DATE, 2005.

Digital Library

[12]

A. Pullini et al., "Bringing NoCs to 65 nm," IEEE Micro, vol. 27, no. 5, 2007.

Digital Library

[13]

D. Mangano et al., "Skew insensitive physical links for network on chip," in Proc. NANONET, 2006.

[14]

I. Miro Panades and A. Greiner, "Bi-synchronous FIFO for synchronous circuit communication well suited for network-on-chip in gals architectures," in Proc. NOCS, 2007.

Digital Library

[15]

T. Felicijan et al., "Asynchronous tdma networks on chip," Royal Philips Electronics, Tech. Rep., 2007.

[16]

A. Hansson et al., "Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip," in Proc. DATE, 2007.

Digital Library

[17]

D. Messerschmitt, "Synchronization in digital system design," IEEE Jour. on Sel. Areas in Comm., vol. 8, no. 8, 1990.

[18]

P. Wielage et al., "Design and DfT of a high-speed area-efficient embedded asynchronous FIFO," in Proc. DATE, 2007.

Digital Library

[19]

E. A. Lee and T. M. Parks, "Dataflow Process Networks," Proc. of the IEEE, vol. 83, no. 5, 1995.

[20]

L. Carloni et al., "Theory of latency-insensitive design," IEEE Trans. on CAD of Int. Circ. and Syst., 2001.

Digital Library

Cited By

Wang PNiknam SMa SWang ZStefanov T(2019)Surf-BlessProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317917(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317917
Picornell TFlich JHernández CDuato J(2019)DCFNoCProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317794(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317794
Venkataramani VKulkarni AMitra TPeh LChen JShrivastava A(2019)SPECTRUM: a software defined predictable many-core architecture for LTE baseband processingProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326352(82-96)Online publication date: 23-Jun-2019
https://dl.acm.org/doi/10.1145/3316482.3326352
Show More Cited By

aelite: a flit-synchronous network on chip with composable and predictable services
1. Hardware

Recommendations

A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip

Networks-on-chip (NoCs) are emerging as a key on-chip communication architecture for multiprocessor systems-on-chip (MPSoCs). Optical communication technologies are introduced to NoCs in order to empower ultra-high bandwidth with low power consumption. ...
PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness

The authors address the design and performance analysis of partial-multiple-bus interconnection networks. They are bus architectures that have evolved from the multiple-bus structure by dividing buses into groups and reducing bus connections. Their ...
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Optical networks-on-chip (ONoCs) are emerging communication architectures that can potentially offer ultrahigh communication bandwidth and low latency to multiprocessor systems-on-chip (MPSoCs). In addition to ONoC architectures, 3-D integrated ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '09: Proceedings of the Conference on Design, Automation and Test in Europe

April 2009

1776 pages

ISBN:9783981080155

General Chairs:
Luca Benini
University of Bologna, IT
,
Giovanni De Micheli
EPFL, CH
,
Program Chairs:
Bashir Al-Hashimi
University of Southampton, UK
,
Wolfgang Mueller
University of Paderborn, DE

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 20 April 2009

Check for updates

Qualifiers

Research-article

Conference

DATE '09

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '09: Design, Automation and Test in Europe

April 20 - 24, 2009

Nice, France

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
103
Total Downloads

Downloads (Last 12 months)1
Downloads (Last 6 weeks)0

Reflects downloads up to 26 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Wang PNiknam SMa SWang ZStefanov T(2019)Surf-BlessProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317917(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317917
Picornell TFlich JHernández CDuato J(2019)DCFNoCProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317794(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317794
Venkataramani VKulkarni AMitra TPeh LChen JShrivastava A(2019)SPECTRUM: a software defined predictable many-core architecture for LTE baseband processingProceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems10.1145/3316482.3326352(82-96)Online publication date: 23-Jun-2019
https://dl.acm.org/doi/10.1145/3316482.3326352
Pourmohseni BWildermann SGlaβ MTeich J(2019)Hard real-time application mapping reconfiguration for NoC-based many-core systemsReal-Time Systems10.1007/s11241-019-09326-y55:2(433-469)Online publication date: 1-Apr-2019
https://dl.acm.org/doi/10.1007/s11241-019-09326-y
Harde TFreier Mvon der Brüggen GChen JOuhammou YRidouard FGrolleau EJan MBehnam M(2018)Configurations and Optimizations of TDMA Schedules for Periodic Packet Communication on Networks on ChipProceedings of the 26th International Conference on Real-Time Networks and Systems10.1145/3273905.3273928(202-212)Online publication date: 10-Oct-2018
https://dl.acm.org/doi/10.1145/3273905.3273928
Hesham SRettkowski JGoehringer DAbd El Ghany M(2017)Survey on Real-Time Networks-on-ChipIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.262361928:5(1500-1517)Online publication date: 1-May-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2623619
Kluge FSchoeberl MUngerer T(2016)Support for the logical execution time model on a time-predictable multicore processorACM SIGBED Review10.1145/3015037.301504713:4(61-66)Online publication date: 3-Nov-2016
https://dl.acm.org/doi/10.1145/3015037.3015047
Psarras ASeitanidis INicopoulos CDimitrakopoulos GNebel WAtienza D(2015)PhaseNoCProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2757066(1090-1095)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2757066
Puffitsch WSørensen RSchoeberl MForget J(2015)Time-division multiplexing vs network calculusProceedings of the 23rd International Conference on Real Time and Networks Systems10.1145/2834848.2834868(289-296)Online publication date: 4-Nov-2015
https://dl.acm.org/doi/10.1145/2834848.2834868
Liu SLu ZJantsch AIvanov AMarculescu DPande PFlich JPattabiraman K(2015)Highway in TDM NoCsProceedings of the 9th International Symposium on Networks-on-Chip10.1145/2786572.2786577(1-8)Online publication date: 28-Sep-2015
https://dl.acm.org/doi/10.1145/2786572.2786577
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten