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RADISH: always-on sound and complete RaDetection in Software and Hardware

Published: 09 June 2012 Publication History
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  • Abstract

    Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforcing both atomicity and determinism. Unfortunately, existing software-only dynamic race detectors are precise but slow; proposals with hardware support offer higher performance but are imprecise. Both precision and performance are necessary to achieve the many advantages always-on dynamic race detection could provide.
    To resolve this trade-off, we propose Radish, a hybrid hardware-software dynamic race detector that is always-on and fully precise. In Radish, hardware caches a principled subset of the metadata necessary for race detection; this subset allows the vast majority of race checks to occur completely in hardware. A flexible software layer handles persistence of race detection metadata on cache evictions and occasional queries to this expanded set of metadata. We show that Radish is correct by proving equivalence to a conventional happens-before race detector.
    Our design has modest hardware complexity: caches are completely unmodified and we piggy-back on existing coherence messages but do not otherwise modify the protocol. Furthermore, Radish can leverage type-safe languages to reduce overheads substantially. Our evaluation of a simulated 8-core Radish processor using PARSEC benchmarks shows runtime overheads from negligible to 2x, outperforming the leading software-only race detector by 2x-37x.

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    Published In

    cover image ACM Conferences
    ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
    June 2012
    584 pages
    ISBN:9781450316422
    • cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 40, Issue 3
      ISCA '12
      June 2012
      559 pages
      ISSN:0163-5964
      DOI:10.1145/2366231
      Issue’s Table of Contents

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    Published: 09 June 2012

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    ISCA '12 Paper Acceptance Rate 47 of 262 submissions, 18%;
    Overall Acceptance Rate 543 of 3,203 submissions, 17%

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    • (2017)Avoiding consistency exceptions under strong memory modelsACM SIGPLAN Notices10.1145/3156685.309227152:9(115-127)Online publication date: 18-Jun-2017
    • (2017)PARSNIPProceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3123939.3123946(490-502)Online publication date: 14-Oct-2017
    • (2017)Avoiding consistency exceptions under strong memory modelsProceedings of the 2017 ACM SIGPLAN International Symposium on Memory Management10.1145/3092255.3092271(115-127)Online publication date: 18-Jun-2017
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