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Latencies of conflicting writes on contemporary multicore architectures

Published: 03 September 2007 Publication History
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  • Abstract

    This paper provides a detailed investigation of latency penalties caused by repeated memory writes to nearby memory cells from different threads in parallel programs. When such writes map to the same corresponding cache lines in multiple processors, one can observe the so called false sharing effect. This effect can unnecessarily hamper parallel code due to the line granularity based cache hierarchy, which is common on contemporary processor architectures. In this contribution, a benchmark allowing for quantitative estimates about the consequences of the false sharing effect, is presented. Results show that multicore architectures with shared cache can reduce unwanted effects of false sharing.

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    Cited By

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    • (2013)Detection of false sharing using machine learningProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.1145/2503210.2503269(1-9)Online publication date: 17-Nov-2013
    • (2011)autopinTransactions on high-performance embedded architectures and compilers III10.5555/1980776.1980792(219-235)Online publication date: 1-Jan-2011
    • (2011)Dynamic cache contention detection in multi-threaded applicationsACM SIGPLAN Notices10.1145/2007477.195268846:7(27-38)Online publication date: 9-Mar-2011
    • Show More Cited By

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    Published In

    cover image Guide Proceedings
    PaCT'07: Proceedings of the 9th international conference on Parallel Computing Technologies
    September 2007
    631 pages
    ISBN:3540739394
    • Editor:
    • Victor Malyshkin

    Sponsors

    • National Scientific Council: National Scientific Council (Taiwan)
    • Microsoft: Microsoft
    • The Russian Fund for Basic Research: The Russian Fund for Basic Research
    • IBM: IBM
    • The Russian Academy of Sciences: The Russian Academy of Sciences

    Publisher

    Springer-Verlag

    Berlin, Heidelberg

    Publication History

    Published: 03 September 2007

    Author Tags

    1. CMP
    2. cache
    3. false sharing
    4. multicore

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    View all
    • (2013)Detection of false sharing using machine learningProceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis10.1145/2503210.2503269(1-9)Online publication date: 17-Nov-2013
    • (2011)autopinTransactions on high-performance embedded architectures and compilers III10.5555/1980776.1980792(219-235)Online publication date: 1-Jan-2011
    • (2011)Dynamic cache contention detection in multi-threaded applicationsACM SIGPLAN Notices10.1145/2007477.195268846:7(27-38)Online publication date: 9-Mar-2011
    • (2011)Dynamic cache contention detection in multi-threaded applicationsProceedings of the 7th ACM SIGPLAN/SIGOPS international conference on Virtual execution environments10.1145/1952682.1952688(27-38)Online publication date: 9-Mar-2011
    • (2011)autopin --- Automated Optimization of Thread-to-Core Pinning on Multicore SystemsProceedings of the 2011 conference on Transactions on High-Performance Embedded Architectures and Compilers III - Volume 659010.1007/978-3-642-19448-1_12(219-235)Online publication date: 1-Jan-2011
    • (2010)Tackling cache-line stealing effects using run-time adaptationProceedings of the 23rd international conference on Languages and compilers for parallel computing10.5555/1964536.1964541(62-76)Online publication date: 7-Oct-2010
    • (2009)Assessing cache false sharing effects by dynamic binary instrumentationProceedings of the Workshop on Binary Instrumentation and Applications10.1145/1791194.1791198(26-33)Online publication date: 12-Dec-2009

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