Browse Theses

The demand for high performance and energy efficient computing has increased the trend of integrating large (hundreds to thousand) number of elements (cores, caches, accelerators, etc.) on to a single chip multi-processor (CMP) for exa-scale computing. The increased trend of system integration in CMPs, combined with the decreasing on-chip feature sizes, place stringent performance and energy requirements on the communication fabric that interconnects the elements on a CMP. As such, on-chip communication networks have become the quintessential component that determine the performance and energy efficiency of the entire computing system or CMP. The contemporary on-chip communication systems such as the mesh based network-on-chip (NoC) topology provide a throughput efficient and an energy efficient solution for the communication between elements on a small CMP. However, the traditional mesh based NoCs do not scale for the exa-scale CMPs (delivering 10 18 floating point operations per second) that consist of hundreds to thousands of cores. The poor scalability of the mesh based NoC for the exa-scale CMPs necessitates the exploration of novel and scalable NoC architectures.

In this dissertation, scalable, high performance and energy efficient NoC architectures for exascale computing CMPs are explored. The use of alternate interconnect types such as wireless interconnects are explored to be used in conjunction with the traditional wired interconnects in novel NoC types for both 2D and 3D integrated circuits (ICs). In addition, novel NoC architectures are investigated for both 2D and 3D ICs that use the network resources efficiently to provide the required NoC performance in terms of throughput, energy efficiency and area efficiency.