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LocusRoute: a parallel global router for standard cells

Author:

Jonathan RoseAuthors Info & Claims

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

Pages 189 - 195

Published: 01 June 1988 Publication History

Abstract

A fast and easily parallelizable global routing algorithm for standard cells and its parallel implementation is presented. LocusRoute is meant to be used as the cost function for a placement algorithm and so this context constrains the structure of the global routing algorithm and its parallel implementation. The router is based on enumerating a subset of all two-bend routes between two points, and results in 16% to 37% fewer total number of tracks than the TimberWolf global router for standard cells [Sech85]. It is comparable in quality to a maze router and an industrial router, but is factor of 10 times or more faster. Three approaches to parallelizing the router are implemented: wire-by-wire parallelism, segment-by-segment and route-by-route. Two of these approaches achieve significant speedup - route-by-route achieves up to 4.6 using eight processors, and wire-by-wire achieves from 5.8 to 7.6 on eight processors.

References

[1]

S. B. Akers, "Routing," Chapter 6 of Design Automation of Digital Systems; Theory and Techniques, M.A. Breuer, Ed., Englewood Cliffs, NJ, Prentice-Hall, 1972.

[2]

T. Blank, M, Stefik, W, VanCleemut, "'A Parallel Bit Map Processor Architecture FOR DA ALGORITHMS," Proc. 18th Design Automation Conference, June 1981, pp. 837-845.

Digital Library

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M.A. Breuer, "Min-Cut Placement," Journal of Design Automation and Fault-Tolerant Computing, Oct 1977, pp 343-362.

[4]

M.A Breuer, K. Shamsa, "A Hardware Router," Journal of Digital Systems, Vol IV, Issue 4, 1981, pp. 393-408.

[5]

M. Hamn, JaM. Kurtzberg, "Placement Techniques," Chapter 4 of Design Automation of Digital Systems; Theory and Techniques, M.A. Breuer, EeL, NI, Prentice-Hall, 1972.

[6]

T. Kambe, T. Okada, T. Chiba, I. Nishioka, "A Global Routing Scheme for Polycell LSI," Proc. ISCAS 1985, pp. 187-190.

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J.B. Kruskal, "On The Shortest Spanning Subtree of a graph and the Traveling Salesman Problem," Proc. Amer. Math. Soc, 7, 1956, pp. 48-50.

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C.Y. Lee, "An Algorithm for Path Connetions and Its Applications," IRE Transactions on Elcctrc~ic Computers, Vol EC-10, pp 346-365, 1961,

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R. Nair,"A Simple Yet Effectiw Technique for Global Wiring," IEEE. Transactions Computer-Aided Design, Vol CAD-6, No. 2, March 1987, pp. 165-172.

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A P-C Ng, P. Raghavan, CA). Thompson, "'A Language for Describing Rectilinear Steiner Tree Conligurations," Proc. 23rd Design Automation Conference, June 1986, pp. 659-662.

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B.T. Preas, "Benchmarks for Cell-Based Layout Systems," Proc. 24rd Design Automation Conference, June 1987, pp. 319-320.

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Ken Roberts used the United Technologies Standard Cell global router on the standard cell benchmark placements. Results were discussed at the 1987 DAC.

[13]

J.S. Rose, W m. Snelgrove, Z.G. Vranesic, "ALTOR: An Automatic Standard Cell Layout Program," Proc. Canadian Conference on VISI, November 1985, pp. 168-173.

[14]

J.S. Rose, W.M. Snelgrove, Z.G. Vranesic, "Parallel Standard Cell Placement Algorithms with Quality Equivalent to Simulated Annealing," IEEE Trans. on CAD, Vol. CAD-7, No. 3, March 1988, pp. 387-396.

[15]

R.A. Ruternbar, T.N. Mudge, D.E. Atkina, "A Class of Cellular Architectures to Support Physical Design Automation," IEEE Trans. on CAD, VoL CAD-3, No, 4, October 1984, pp, 264-278,

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C. Sechen, A. Sangiovanni-Vincentelli, "The Timberwolf Placement and Routing Package," IEEE JSSC, Vol. SC-20, No, 2, April 1985, pp 510-522. pp. 432-439.

Cited By

Olszewski MAnsel JAmarasinghe S(2009)KendoACM SIGARCH Computer Architecture News10.1145/2528521.150825637:1(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/2528521.1508256
Olszewski MAnsel JAmarasinghe S(2009)KendoACM SIGPLAN Notices10.1145/1508284.150825644:3(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508284.1508256
Olszewski MAnsel JAmarasinghe SSoffa MIrwin M(2009)KendoProceedings of the 14th international conference on Architectural support for programming languages and operating systems10.1145/1508244.1508256(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508244.1508256
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LocusRoute: a parallel global router for standard cells

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cover image ACM Conferences

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

June 1988

730 pages

ISBN:0818688645

Chairmen:
Dennis W. Shaklee
AT&T/ISL, Denver, CO
,
A. Richard Newton
Univ. of California, Berkeley

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SIGDA: ACM Special Interest Group on Design Automation
IEEE: Institute of Electrical and Electronics Engineers

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 June 1988

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DAC88

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SIGDA
IEEE

DAC88: Design Automation Conference

June 12 - 15, 1988

New Jersey, Atlantic City, USA

Acceptance Rates

DAC '88 Paper Acceptance Rate 125 of 400 submissions, 31%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Olszewski MAnsel JAmarasinghe S(2009)KendoACM SIGARCH Computer Architecture News10.1145/2528521.150825637:1(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/2528521.1508256
Olszewski MAnsel JAmarasinghe S(2009)KendoACM SIGPLAN Notices10.1145/1508284.150825644:3(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508284.1508256
Olszewski MAnsel JAmarasinghe SSoffa MIrwin M(2009)KendoProceedings of the 14th international conference on Architectural support for programming languages and operating systems10.1145/1508244.1508256(97-108)Online publication date: 7-Mar-2009
https://dl.acm.org/doi/10.1145/1508244.1508256
Rauber TRünger G(2000)A Transformation Approach to Derive Efficient Parallel ImplementationsIEEE Transactions on Software Engineering10.1109/32.84449226:4(315-339)Online publication date: 1-Apr-2000
https://dl.acm.org/doi/10.1109/32.844492
Xing ZChandy JBanerjee P(1997)Parallel Global Routing Algorithms for Standard CellsProceedings of the 11th International Symposium on Parallel Processing10.5555/645607.661353Online publication date: 1-Apr-1997
https://dl.acm.org/doi/10.5555/645607.661353
Torrellas JLam HHennessy J(1994)False Sharing and Spatial Locality in Multiprocessor CachesIEEE Transactions on Computers10.1109/12.28629943:6(651-663)Online publication date: 1-Jun-1994
https://dl.acm.org/doi/10.1109/12.286299
Swartz WSechen CLightner MJess J(1993)A new generalized row-based global routerProceedings of the 1993 IEEE/ACM international conference on Computer-aided design10.5555/259794.259875(491-498)Online publication date: 7-Nov-1993
https://dl.acm.org/doi/10.5555/259794.259875
Cheriton DGoosen HHolbrook HMachanick P(1993)Restructuring a parallel simulation to improve cache behavior in a shared-memory multiprocessorACM SIGSIM Simulation Digest10.1145/174134.15848023:1(159-162)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/174134.158480
Cheriton DGoosen HHolbrook HMachanick P(1993)Restructuring a parallel simulation to improve cache behavior in a shared-memory multiprocessorProceedings of the seventh workshop on Parallel and distributed simulation10.1145/158459.158480(159-162)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/158459.158480
Gharachorloo KGupta AHennessy J(1992)Hiding memory latency using dynamic scheduling in shared-memory multiprocessorsACM SIGARCH Computer Architecture News10.1145/146628.13967820:2(22-33)Online publication date: 1-Apr-1992
https://dl.acm.org/doi/10.1145/146628.139678
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