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A digit-serial silicon compiler

Authors:

Richard I. Hartley,

Peter F. CorbettAuthors Info & Claims

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

Pages 646 - 649

Published: 01 June 1988 Publication History

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Abstract

A new silicon compiler is described, called PARSIFAL (not an acronym). It constructs chips with a data flow architecture in which data is passed in a digit-wide pipeline from one computational element to the next. The size of a digit may be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of digit-size usually gives the most efficient chips in terms of throughput per unit area.

References

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Hartley, Richard and Jasica J. Behavioral to Structural Translation in a Bit-serial Silicon Compiler. To aIveat in IEEE Trans. on CAD.

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Chatterjee ARoy RDunlop A(1993)An architectural transformation program for optimization of digital systems by multi-level decompositionProceedings of the 30th international Design Automation Conference10.1145/157485.164923(343-348)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164923
Roy RChatterjee APatel JAbraham Jd'Abreu MTrevillyan LLightner M(1992)Automatic test generation for linear digital systems with bi-level search using matrix transform methodsProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304096(224-228)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304096
Chatterjee AHartley RSmith R(1991)A new simultaneous circuit partitioning and chip placement approach based on simulated annealingProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123221(36-39)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123221
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A digit-serial silicon compiler

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Published In

DAC '88: Proceedings of the 25th ACM/IEEE Design Automation Conference

June 1988

730 pages

ISBN:0818688645

Chairmen:
Dennis W. Shaklee
AT&T/ISL, Denver, CO
,
A. Richard Newton
Univ. of California, Berkeley

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 June 1988

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DAC88: Design Automation Conference

June 12 - 15, 1988

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DAC '88 Paper Acceptance Rate 125 of 400 submissions, 31%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Chatterjee ARoy RDunlop A(1993)An architectural transformation program for optimization of digital systems by multi-level decompositionProceedings of the 30th international Design Automation Conference10.1145/157485.164923(343-348)Online publication date: 1-Jul-1993
https://dl.acm.org/doi/10.1145/157485.164923
Roy RChatterjee APatel JAbraham Jd'Abreu MTrevillyan LLightner M(1992)Automatic test generation for linear digital systems with bi-level search using matrix transform methodsProceedings of the 1992 IEEE/ACM international conference on Computer-aided design10.5555/304032.304096(224-228)Online publication date: 8-Nov-1992
https://dl.acm.org/doi/10.5555/304032.304096
Chatterjee AHartley RSmith R(1991)A new simultaneous circuit partitioning and chip placement approach based on simulated annealingProceedings of the 27th ACM/IEEE Design Automation Conference10.1145/123186.123221(36-39)Online publication date: 3-Jan-1991
https://dl.acm.org/doi/10.1145/123186.123221
Hartley RWelles II KHartman MChatterjee ADelano PMolnar BRafferty C(1991)A Rapid-Prototyping Environment for Digital-Signal ProcessorsIEEE Design & Test10.1109/54.820358:2(11-25)Online publication date: 1-Apr-1991
https://dl.acm.org/doi/10.1109/54.82035
Hartley RWelles KHartman MDelano PChatterjee AAdshead GJess J(1990)Rapid prototyping using high density interconnectsProceedings of the conference on European design automation10.5555/949970.950069(439-443)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950069
Krämer HRosenstiel WAdshead GJess J(1990)System synthesis using behavioural descriptionsProceedings of the conference on European design automation10.5555/949970.950033(277-282)Online publication date: 12-Mar-1990
https://dl.acm.org/doi/10.5555/949970.950033
Smith WDuff DDragomirecky MCaldwell JHartman MJasica Jd'Abreu MThomas D(1989)FACE core environment: the model and its application in CAE/CAD tool developmentProceedings of the 26th ACM/IEEE Design Automation Conference10.1145/74382.74460(466-471)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/74382.74460
Casavant Ad'Abreu MDragomirecky MDuff DJasica JHartman MHwang KSmit W(1989)A Synthesis Environment for Designing DSP SystemsIEEE Design & Test10.1109/54.191336:2(35-44)Online publication date: 1-Mar-1989
https://dl.acm.org/doi/10.1109/54.19133

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Pipelined area-efficient digit serial divider

Low-power digit-serial and bit-serial dsp systems

Digit-Serial Complex-Number Multipliers on FPGAs

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Pipelined area-efficient digit serial divider

Low-power digit-serial and bit-serial dsp systems

Digit-Serial Complex-Number Multipliers on FPGAs

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