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TIDBITS: speedup via time-delay bit-slicing in ALU design for VLSI technology

Published: 01 June 1985 Publication History
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    References

    [1]
    [1] R. P. Brent and H. T. Kung, "A Regular Layout for Parallel Adders," IEEE Transaction on Computers, vol. C-31, pp. 260-264, March 1982.
    [2]
    [2] C. Mead and L. Conway, Introduction to VLSI systems . Reading: Addison-Wesley Publishing Company, 1980.
    [3]
    [3] P. M. Kogge, The Architecture of Pipelined Computers. New York, N. Y.: Hemisphere Publishing Corporation, 1981, p. 10.
    [4]
    [4] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing. Englewood Cliffs, New Jersey: Prentice-Hall, 1975.
    [5]
    [5] J.-Y. Jou and Jacob Abraham, "Fault-Tolerant Matrix Operations on Multiple Processor Systems using Weighted Checksums," Proc. SPIE Conf., vol. 495, pp. 94-101, Aug. 1984.
    [6]
    [6] J. D. Ullman, Computational Aspects of VLSI. Rockville, Maryland: Computer Science Press, 1984.
    [7]
    [7] J. P. Hayes, Computer Architecture and Organization. New York, N. Y.: McGraw-Hill, 1978. p. 107.
    [8]
    [8] W. Karplus and D. Cohen, "Architectural and Software Issues in the Design and Application of Peripheral Array Processors," Computer, vol. 14, pp. 11- 17, September 1981.

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    1. TIDBITS: speedup via time-delay bit-slicing in ALU design for VLSI technology

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        cover image ACM Conferences
        ISCA '85: Proceedings of the 12th annual international symposium on Computer architecture
        June 1985
        428 pages
        ISBN:0818606347

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        IEEE Computer Society Press

        Washington, DC, United States

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        Published: 01 June 1985

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        ISCA85: International Symposium on Computer Architecture
        June 17 - 19, 1985
        Massachusetts, Boston, USA

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        View all
        • (2003)Macro-op SchedulingProceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956563Online publication date: 3-Dec-2003
        • (2019)Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715045(924-927)Online publication date: Mar-2019
        • (2003)Macro-op SchedulingProceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture10.5555/956417.956563Online publication date: 3-Dec-2003
        • (2003)Macro-op scheduling: relaxing scheduling loop constraints22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)10.1109/MICRO.2003.1253202(277-288)Online publication date: 2003
        • (1998)Digital circuit applications of resonant tunneling devicesProceedings of the IEEE10.1109/5.66354486:4(664-686)Online publication date: Apr-1998

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