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A systematic analysis of reuse strategies for design of electronic circuits

Published: 23 February 1998 Publication History

Abstract

In this paper a number of reuse approaches for circuit design are analysed. Based on this analysis an algebraic core model for discussion of a general reuse strategy is proposed. Using this model, the aim is to classify different reuse approaches for circuit design, to compare the applied terms and definitions, and to formulate classes of typical reuse tasks. In a practical application with focus on retrieval and parameterisation techniques, this model is on the way to being applied to DSP design issues.

References

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Altmeyer, J.; Ohnsorge, St.; Sch~rmann, B.: Reuse of Design Objects in CAD Frameworks. Proceedings of the International Conference on Computer Aided Design, San Jose, California, 1994.
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Bergmann, R.,: Effizientes Probleml~sen durch flexible Wiederverwendung von F~llen auf verschiedenen Abstraktionsebenen. Dissertation Universit~t Kaiserslautern, 1996.
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Conradi, P.: Information Model of a Compound Graph Presentation for System and Architecture Level Design. EURO-DAC '95, pp. 22-27.
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Frakes, W.B.; Fox, C.J.: Sixteen questions about software reuse. Communications of the ACM, 38(6), pp. 75-87, June 1995.
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Jerraya, A.A.; Ding, H.; Kission, P.; Rahmouni, M.: Behavioral Synthesis and Component Reuse with VHDL. Kluwer Academic Publishers, Boston/ Lon-don/ Dortrecht, 1997.
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Jha, P.; Dutt, N.D.: Design Reuse Through High- Level Library Mapping. European Design and Test Conference, Paris, 1995, pp. 345-350.
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Kission, P.; Ding, H.; Jerraya, A.A.: VHDL Based Design Methodology for Hierarchy and Component Re-Use. EURO-DAC '95, pp. 470-475.
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Koegst, M.; Conradi, P.; Garte, D.; Wahl, M.: Analysis and Classification of Reuse Strategies and Tasks for the Circuit Design, IWLAS'97, Grenoble.
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Cited By

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  • (2004)Generic integration infrastructure for IP-based design processes and tools with a unified XML formatIntegration, the VLSI Journal10.1016/j.vlsi.2004.01.00137:4(289-321)Online publication date: 1-Sep-2004
  • (2001)Functional abstraction driven design space exploration of heterogeneous programmable architecturesProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500061(256-261)Online publication date: 30-Sep-2001
  • (2000)Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and MegacellsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855855Online publication date: 20-Mar-2000
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cover image ACM Conferences
DATE '98: Proceedings of the conference on Design, automation and test in Europe
February 1998
940 pages

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IEEE Computer Society

United States

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Published: 23 February 1998

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DATE98
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DATE98: Design, Automation & Test in Europe
February 23 - 26, 1998
Le Palais des Congrés de Paris, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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View all
  • (2004)Generic integration infrastructure for IP-based design processes and tools with a unified XML formatIntegration, the VLSI Journal10.1016/j.vlsi.2004.01.00137:4(289-321)Online publication date: 1-Sep-2004
  • (2001)Functional abstraction driven design space exploration of heterogeneous programmable architecturesProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500061(256-261)Online publication date: 30-Sep-2001
  • (2000)Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and MegacellsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855855Online publication date: 20-Mar-2000
  • (2000)Formalized three-layer system-level reuse model and methodology for embedded data-dominated applicationsProceedings of the conference on Design, automation and test in Europe10.1145/343647.343711(92-98)Online publication date: 1-Jan-2000
  • (2000)Linking codesign and reuse in embedded systems designProceedings of the eighth international workshop on Hardware/software codesign10.1145/334012.334030(93-97)Online publication date: 1-May-2000
  • (1999)An efficient reuse system for digital circuit designProceedings of the conference on Design, automation and test in Europe10.1145/307418.307444(9-es)Online publication date: 1-Jan-1999

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