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A VHDL reuse workbench

Authors:

G. Lehmann,

K. Müller-Glaser,

B. WunderAuthors Info & Claims

EURO-DAC '96/EURO-VHDL '96: Proceedings of the conference on European design automation

Pages 412 - 417

Published: 20 September 1996 Publication History

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Bautista TNúñez A(2000)Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and MegacellsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855855Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855855
Schaumont PCmar RVernalde SEngels MBolsens I(1999)Hardware reuse at the behavioral levelProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.310058(784-789)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.310058
Reutter ARosenstiel W(1999)An efficient reuse system for digital circuit designProceedings of the conference on Design, automation and test in Europe10.1145/307418.307444(9-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307444
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A VHDL reuse workbench
1. Hardware

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The "Reuse without Reusers" SyndromeThe problems of low productivity, late delivery and poor software quality are, unfortunately, characteristic of the software industry (Horowitz and Munson 1989). Increasingly, software developers are looking towards ...
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Published In

EURO-DAC '96/EURO-VHDL '96: Proceedings of the conference on European design automation

September 1996

604 pages

ISBN:081867573X

Chairmen:
Graham Symonds
Viewlogic Systems Ltd., Bracknell, Berkshire, UK
,
Wolfgang Nebel
Carl-von-Ossietzky Univ., Oldenburg, Germany

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 20 September 1996

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EuroDAC95

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SI-G
EDAC
SIGDA
IEEE-CS
IFIP

EuroDAC95: European Design Automation Conference

Geneva, Switzerland

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June 22 - 26, 2025

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Bautista TNúñez A(2000)Synthesis Experiments and Performance Metrics for Evaluating the Quality of IP Blocks and MegacellsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855855Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855855
Schaumont PCmar RVernalde SEngels MBolsens I(1999)Hardware reuse at the behavioral levelProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.310058(784-789)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.310058
Reutter ARosenstiel W(1999)An efficient reuse system for digital circuit designProceedings of the conference on Design, automation and test in Europe10.1145/307418.307444(9-es)Online publication date: 1-Jan-1999
https://dl.acm.org/doi/10.1145/307418.307444
Koegst MConradi PGarte DWahl MDewilde PRammig FMusgrave G(1998)A systematic analysis of reuse strategies for design of electronic circuitsProceedings of the conference on Design, automation and test in Europe10.5555/368058.368152(292-296)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368152
Lehmann GWunder BMüller-Glaser KRutenbar ROtten R(1997)Basic concepts for an HDL reverse engineering tool-setProceedings of the 1996 IEEE/ACM international conference on Computer-aided design10.5555/244522.244544(134-141)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.5555/244522.244544

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P4-To-VHDL

Viewpoint-centred reuse: bridging the gap between reusability and the needs of the reuser

A Tutorial Introduction to VHDL Programming

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P4-To-VHDL

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A Tutorial Introduction to VHDL Programming

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