R. K. Gupta and S. Y. Liao. Using a programming language for digital system design. IEEE Design and Test o/ Computers, pages 72 - 80, April-June 1997.

Digital Library

Google Scholar

[5]

Ocapi Homepage. http://www.imec.be/ocapi.

Google Scholar

[6]

G. Lehmann, B. Wunder, and K. Muller-Glaser. A vhdl reuse workbench. In Proc. EDAC 1996, pages 412-417.

Digital Library

Google Scholar

[7]

G. Martin. Design methodologies for system level ip. In Proc. DATE 1998, pages 286-302.

Digital Library

Google Scholar

[8]

P. Schaumont, S. Vernalde, L. Rijnders, M. Engels, and I. Bolsens. A programming environment for the design of complex high speed asics. In Proceedings 35th Design Automation Conference, pages 315 - 320, San Francisco, CA, 1998.

Digital Library

Google Scholar

[9]

C. Scl~neider and W. Ecker. Stepwise refinement of behavioral vhdl specifications by separation of synchronization and functionality. In Proc. EURODAC 1996, pages 509-514.

Digital Library

Google Scholar

[10]

G. Schumacher, W. Nebel, and C. von Ossietzky. Objectoriented modeling of parallel hardware systems. In Proc. DATE 19.98, pages 234-241.

Digital Library

Google Scholar

[11]

S. Vercauteren and Bill Lin. Hardware/software Communication and System Integration for Embedded Architectures. Design Automation o/Embedded Systems, Kluwer Academic Publishers, 2:1-24, 1997.

Google Scholar

[12]

C. Weiler, U. Kebschull, and W. Rosenstiel. C++ base classes for specification, simulation and partitioning of a hardware/software system. In Proc. ASP-DA C 1995, CHDL 1.995, VLSI 1995, pages 777-784.

Google Scholar

Cited By

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Eberle W(2008)Conclusions and Further ResearchWireless Transceiver Systems Design10.1007/978-0-387-74516-9_8(233-247)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_8
Eberle W(2008)Methodologies for Transceiver DesignWireless Transceiver Systems Design10.1007/978-0-387-74516-9_7(201-232)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_7
Eberle W(2008)Design Space Exploration for TransmittersWireless Transceiver Systems Design10.1007/978-0-387-74516-9_6(175-199)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_6
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Index Terms

Hardware reuse at the behavioral level
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

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Eberle W(2008)Conclusions and Further ResearchWireless Transceiver Systems Design10.1007/978-0-387-74516-9_8(233-247)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_8
Eberle W(2008)Methodologies for Transceiver DesignWireless Transceiver Systems Design10.1007/978-0-387-74516-9_7(201-232)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_7
Eberle W(2008)Design Space Exploration for TransmittersWireless Transceiver Systems Design10.1007/978-0-387-74516-9_6(175-199)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_6
Eberle W(2008)Digital Compensation Techniques for Receiver Front-EndsWireless Transceiver Systems Design10.1007/978-0-387-74516-9_5(133-173)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_5
Eberle W(2008)Efficient Digital VLSI Signal Processing for OFDMWireless Transceiver Systems Design10.1007/978-0-387-74516-9_4(79-132)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_4
Eberle W(2008)Specification for a Wireless LAN TerminalWireless Transceiver Systems Design10.1007/978-0-387-74516-9_3(45-77)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_3
Eberle W(2008)The System Design ProcessWireless Transceiver Systems Design10.1007/978-0-387-74516-9_2(17-43)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_2
Eberle W(2008)IntroductionWireless Transceiver Systems Design10.1007/978-0-387-74516-9_1(1-15)Online publication date: 2008
https://doi.org/10.1007/978-0-387-74516-9_1
Wagner FCesário WJerraya A(2007)Hardware/software IP integration using the ROSES design environmentACM Transactions on Embedded Computing Systems10.1145/1275986.12759896:3(17-es)Online publication date: 1-Jul-2007
https://dl.acm.org/doi/10.1145/1275986.1275989
Van Court THerbordt M(2007)Families of FPGA-based accelerators for approximate string matchingMicroprocessors & Microsystems10.1016/j.micpro.2006.04.00131:2(135-145)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1016/j.micpro.2006.04.001
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