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Hardware/software IP integration using the ROSES design environment

Published: 01 July 2007 Publication History

Abstract

Considering current time-to-market pressures, IP reuse is mandatory for the design of complex embedded systems-on-chip (SoC). The integration of IP components into a given design is the most complex task in the whole reuse process. This paper describes the IP integration approach implemented in the ROSES design environment, which presents a unique combination of features that enhance IP reuse: automatic assembly of interfaces between heterogeneous software and hardware IP components; easy adaptation to different on-chip communication structures and bus and core standards; generation of customized and minimal OSs for programmable components; and an architecture-independent high-level API embedded into SystemC that makes application software independent from system implementation. Application code is written by using communication functions available in this API. ROSES automatically assembles wrappers that implement these functions, such that the application code does not need to be modified in order to run in the final synthesized system.

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  • (2014)Optimized memory access support for data layout conversion on heterogeneous multi-core systems2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)10.1109/ESTIMedia.2014.6962353(128-137)Online publication date: Oct-2014
  • (2011)Related WorkMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_4(49-54)Online publication date: 10-Jan-2011
  • (2011)Principles of Design Space ExplorationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_3(23-47)Online publication date: 10-Jan-2011
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Published In

cover image ACM Transactions on Embedded Computing Systems
ACM Transactions on Embedded Computing Systems  Volume 6, Issue 3
July 2007
138 pages
ISSN:1539-9087
EISSN:1558-3465
DOI:10.1145/1275986
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Association for Computing Machinery

New York, NY, United States

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Publication History

Published: 01 July 2007
Published in TECS Volume 6, Issue 3

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Author Tags

  1. IP integration
  2. Systems-on-chip

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View all
  • (2014)Optimized memory access support for data layout conversion on heterogeneous multi-core systems2014 IEEE 12th Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia)10.1109/ESTIMedia.2014.6962353(128-137)Online publication date: Oct-2014
  • (2011)Related WorkMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_4(49-54)Online publication date: 10-Jan-2011
  • (2011)Principles of Design Space ExplorationMultiprocessor Systems on Chip10.1007/978-1-4419-8153-0_3(23-47)Online publication date: 10-Jan-2011
  • (2010)Concept-based partitioning for large multidomain multifunctional embedded systemsACM Transactions on Design Automation of Electronic Systems10.1145/1754405.175440715:3(1-41)Online publication date: 10-Jun-2010
  • (2008)Automatic Integration of Non-Bus Hardware IP into SoC-Platforms for Use by SoftwareProceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing - Volume 0110.1109/EUC.2008.140(59-65)Online publication date: 17-Dec-2008

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