Article

BIST for Phase-Locked Loops in Digital Applications

Authors:

Stephen Sunter,

Aubin RoyAuthors Info & Claims

ITC '99: Proceedings of the 1999 IEEE International Test Conference

Page 532

Published: 28 September 1999 Publication History

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Abstract

Phase-locked loops (PLLs) are an essential buildingblock of most digital and mixed-signal ICs. This paperdescribes a built-in self-test (BIST) circuit that tests thekey analog parameters of PLLs, using only logic gatesthat can be synthesized from a hardware descriptionlanguage (HDL). The parameters tested include lockrange, lock time, RMS jitter, and loop gain (from whichthe natural frequency is calculated). Experimentalwaveforms and results are shown for a 200 MHz PLLwhich uses a phase-frequency detector. Test time istypically 10 ms, much faster than for conventional testing.

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A. Hajimiri, et al, "Jitter and Phase Noise in Ring Oscillators", IEEE J. Solid-State Circuits, vol. 34, pp. 790-804, June 1999.

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Lee YYang CCheng NChen JDe Micheli GAl-Hashimi BMueller WMacii E(2010)An embedded wide-range and high-resolution CLOCK jitter measurement circuitProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871321(1637-1640)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871321
Jiang SCheng KJian P(2009)A 2.5-GHz built-in jitter measurement system in a serial-link transceiverIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200647617:12(1698-1708)Online publication date: 1-Dec-2009
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Published In

ITC '99: Proceedings of the 1999 IEEE International Test Conference

September 1999

ISBN:0780357531

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IEEE Computer Society

United States

Publication History

Published: 28 September 1999

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Lee YYang CCheng NChen JDe Micheli GAl-Hashimi BMueller WMacii E(2010)An embedded wide-range and high-resolution CLOCK jitter measurement circuitProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871321(1637-1640)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871321
Jiang SCheng KJian P(2009)A 2.5-GHz built-in jitter measurement system in a serial-link transceiverIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200647617:12(1698-1708)Online publication date: 1-Dec-2009
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Bordoley DNguyen HSoma M(2005)A statistical study of the effectiveness of BIST jitter measurement techniquesProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129618(100-107)Online publication date: 31-May-2005
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Egan TMourad S(2005)Design-for-testability for embedded delay-locked loopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2005.85362213:8(984-988)Online publication date: 1-Aug-2005
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Xia TZheng HLi JGinawi A(2005)Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier OscillatorsProceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design10.1109/ISVLSI.2005.66(218-223)Online publication date: 11-May-2005
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Sehgal ALiu FOzev SChakrabarty K(2005)Test Planning for Mixed-Signal SOCs with Wrapped Analog CoresProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.303(50-55)Online publication date: 7-Mar-2005
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Chan ARoberts G(2004)A jitter characterization system using a component-invariant vernier delay lineIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2003.82053112:1(79-95)Online publication date: 1-Jan-2004
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Burbidge MTijou JRichardson A(2003)Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked LoopsProceedings of the conference on Design, Automation and Test in Europe - Volume 110.5555/789083.1022776Online publication date: 3-Mar-2003
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