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A Library of Parameterized Floating-Point Modules and Their Use

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FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

September 2002

Pages 657 - 666

Published: 02 September 2002 Publication History

Abstract

We present a parameterized floating-point library for use with reconfigurable hardware. Our format is both general and flexible. All IEEE formats are a subset of our format, as are all previously published floating-point formats for reconfigurable hardware. We have developed a library of fully parameterized hardware modules for format control, arithmetic operations and conversion to and from any fixed-point format. The format converters allow for hybrid implementations that combine both fixed and floating-point calculations. This permits the designer to choose between the increased range of floating-point and the increased precision of fixed-point within the same application. We illustrate the use of this library with a hybrid implementation of the K-means clustering algorithm applied to multispectral satellite images.

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Cited By

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Tang SLemieux GConstantinides GChen D(2015)Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689146(276-276)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689146
de Dinechin FEcheverría PLópez-Vallejo MPasca B(2013)Floating-Point Exponentiation Units for Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574476:1(1-15)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1145/2457443.2457447
Chen DSingh D(2013)Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applicationsACM Transactions on Architecture and Code Optimization10.1145/2400682.24007029:4(1-25)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400702
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A Library of Parameterized Floating-Point Modules and Their Use
1. Security and privacy
  1. Software and application security
    1. Software reverse engineering

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FPL '02: Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

September 2002

1181 pages

ISBN:3540441085

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 02 September 2002

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Tang SLemieux GConstantinides GChen D(2015)Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/2684746.2689146(276-276)Online publication date: 22-Feb-2015
https://dl.acm.org/doi/10.1145/2684746.2689146
de Dinechin FEcheverría PLópez-Vallejo MPasca B(2013)Floating-Point Exponentiation Units for Reconfigurable ComputingACM Transactions on Reconfigurable Technology and Systems10.1145/2457443.24574476:1(1-15)Online publication date: 1-May-2013
https://dl.acm.org/doi/10.1145/2457443.2457447
Chen DSingh D(2013)Profile-guided floating- to fixed-point conversion for hybrid FPGA-processor applicationsACM Transactions on Architecture and Code Optimization10.1145/2400682.24007029:4(1-25)Online publication date: 20-Jan-2013
https://dl.acm.org/doi/10.1145/2400682.2400702
Jaiswal MCheung R(2013)VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba TechniqueCircuits, Systems, and Signal Processing10.1007/s00034-012-9457-332:1(15-27)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1007/s00034-012-9457-3
Le Lann CBoland DConstantinides G(2011)The Krawczyk algorithmProceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications10.5555/1987535.1987574(287-295)Online publication date: 23-Mar-2011
https://dl.acm.org/doi/10.5555/1987535.1987574
Wang XLeeser M(2010)VFloatACM Transactions on Reconfigurable Technology and Systems10.1145/1839480.18394863:3(1-34)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1145/1839480.1839486
Hemmert KUnderwood K(2010)Fast, Efficient Floating-Point Adders and Multipliers for FPGAsACM Transactions on Reconfigurable Technology and Systems10.1145/1839480.18394813:3(1-30)Online publication date: 1-Sep-2010
https://dl.acm.org/doi/10.1145/1839480.1839481
Lienhart GKugel AMänner R(2006)Rapid development of high performance floating-point pipelines for scientific simulationProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1899135(191-191)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1899135
Meng YBrown AIltis RSherwood TLee HKastner RJoyner WMartin GKahng A(2005)MP coreProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065658(297-302)Online publication date: 13-Jun-2005
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deLorimier MDeHon ASchmit HWilton S(2005)Floating-point sparse matrix-vector multiply for FPGAsProceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays10.1145/1046192.1046203(75-85)Online publication date: 20-Feb-2005
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Cited By

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Decimal Floating-Point Multiplication

Hardware Designs for Decimal Floating-Point Addition and Related Operations

Fast decimal floating-point division

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