Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)
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Abstract
Floating point implementation has been a hot topic in recent FPGA research. This paper describes a method to optimize area of combined floating point and integer arithmetic unit through sharing the largest component in each operation on an FPGA. Specifically, the operations included are: addition, subtraction, multiplication, division, shift left/right, rotate left/right, as well as integer-to-floating-point and floating-point-to-integer conversion. The resource usage for the fused unit is compared with the segregated units that are multiplexed. Result shows a significant area reduction achieved using this technique with minimal performance penalty.
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Index Terms
- Area Optimization of Arithmetic Units by Component Sharing for FPGAs (Abstract Only)
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Published In
February 2015
292 pages
ISBN:9781450333153
DOI:10.1145/2684746
- General Chair:
- George A. Constantinides,
- Program Chair:
- Deming Chen
Copyright © 2015 Owner/Author.
Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.
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Published: 22 February 2015
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FPGA '15
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FPGA '15: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
February 22 - 24, 2015
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FPGA '15 Paper Acceptance Rate 20 of 102 submissions, 20%;
Overall Acceptance Rate 125 of 627 submissions, 20%
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