Article

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors

Authors:

Sri Parameswaran,

Jörg HenkelAuthors Info & Claims

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Page 291

Published: 09 November 2003 Publication History

Abstract

This paper presents the INSIDE system that rapidly searchesthe design space for extensible processors, given area and performance constraints of an embedded application, while minimizing the design turn-around-time. Our system consists ofa) a methodology to determine which code segments are mostsuited for implementation as a set of extensible instructions,b) a heuristic algorithm to select pre-configured extensibleprocessors as well as extensible instructions (library), and c)an estimation tool which rapidly estimates the performance ofan application on a generated extensible processor. By selecting the right combination of a processor core plus extensible instructions, we achieve a performance increase on average of 2.03x (up to 7x) compared to the base processor core at aminimum hardware overhead of 25% on average.

References

[1]

{1} Arctangent processor. ARC International. (http://www.arc.com).

[2]

{2} Asip-meister. (http://www.eda-meister.org/asip-meister/).

[3]

{3} Design compiler. Synopsys Inc. (http://www.synopsys.com).

[4]

{4} Jazz dsp. Improv Systems Inc. (http://www.improvsys.com).

[5]

{5} Lisatek. CoWare Inc. (http://www.coware.com).

[6]

{6} Sp-5flex dsp core. 3DSP Corp. (http://www.3dsp.com).

[7]

{7} Xtensa processor. Tensilica Inc. (http://www.tensilica.com).

[8]

{8} A. Alomary, T. Nakata, Y. Honma, M. Imai, and N. Hikichi. An asip instruction set optimization algorithm with functional module sharing constraint. In DAC, pages 526-532. IEEE Computer Society Press, 1993.

Digital Library

[9]

{9} N. Binh, M. Imai, and Y. Takeuchi. A performance maximization algorithm to design asips under the constraint of chip area including ram and rom size. In ASP-DAC, 1998.

[10]

{10} P. Brisk, A. Kaplan, R. Kastner, and M. Sarrafzadeh. Instruction generation and regularity extraction for reconfigurable processors. In CASES, 2002.

Digital Library

[11]

{11} N. Cheung, J. Henkel, and S. Parameswaran. Rapid configuration & instruction selection for an asip: A case study. In DATE, 2003.

Digital Library

[12]

{12} M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freeman and Co, 1979.

Digital Library

[13]

{13} R. Gonzalez. Xtensa: A configurable and extensible processor. IEEE Micro, 2000.

Digital Library

[14]

{14} M. Gschwind. Instruction set selection for asip design. In 7th international workshop on Hardware/software codesign, pages 7-11. ACM Press, 1999.

Digital Library

[15]

{15} T. V. K. Gupta, P. Sharma, M. Balakrishnan, and S. Malik. Processor evaluation in an embedded systems design environment. In VLSI Design, pages 98-103, 2000.

Digital Library

[16]

{16} M. Imai, N. Binh, and A. Shiomi. A new hw/sw partitioning algorithm for synthesizing the highest performance pipelined asips with multiple identical fus. In EURO-VHDL, pages 126-131. IEEE Computer Society Press, 1996.

Digital Library

[17]

{17} M. K. Jain, L. Wehmeyer, S. Steinke, P. Marwedel, and M. Balakrishnan. Evaluating register file size in asip design. In CODES, pages 109-114, 2001.

Digital Library

[18]

{18} R. Kastner, S. Ogrenci-Memik, E. Bozorgzadeh, and M. Sarrafzadeh. Instruction generation for hybrid reconfigurable systems. In ICCAD, 2001.

Digital Library

[19]

{19} V. Kathail, shail Aditya, R. Schreiber, B. R. Rau, D. C. Cronquist, and M. Sivaraman. Pico: Automatically designing custom computers. Computer, 35(9):39-47, Sept 2002.

Digital Library

[20]

{20} S. Kobayashi, H. Mita, Y. Takeuchi, and M. Imai. Design space exploration for dsp applications using the asip development system peas-iii. In ASSP, pages 3168-3171, 2002.

[21]

{21} C. Lee, M. Potkonjak, and W. H. Mangione-Smith. Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In International Symposium on Microarchitecture, pages 330-335, 1997.

Digital Library

[22]

{22} J. Lee, K. Choi, and N. Dutt. Efficient instruction encoding for automatic instruction set desifn of configurable asips. In ICCAD, 2002.

Digital Library

[23]

{23} F. Sun, S. Ravi, A. Raghunathan, and N. Jha. Synthesis of custom processors based on extensible platforms. In ICCAD, 2002.

Digital Library

[24]

{24} J.-H. Yang, B.-W. Kim, et al. Metacore: an application specific dsp development system. In DAC, pages 800-803, 1998.

Digital Library

[25]

{25} Q. Zhao, B. Mesman, and T. Basten. Practical instruction set design and compiler retargetability using static resource models. In DATE, pages 1021-1026, 2002.

Digital Library

Cited By

Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Bordoloi UHuynh HChakraborty SMitra T(2009)Evaluating design trade-offs in customizable processorsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629978(244-249)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629978
Galanis MDimitroulakos GTragoudas SGoutis C(2008)Speedups in embedded systems with a high-performance coprocessor datapathACM Transactions on Design Automation of Electronic Systems10.1145/1255456.125547212:3(1-22)Online publication date: 22-May-2008
https://dl.acm.org/doi/10.1145/1255456.1255472
Show More Cited By

Index Terms

INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors

Recommendations

An inside look at the Z80,000 CPU: Zilog's new 32-bit microprocessor
AFIPS '84: Proceedings of the July 9-12, 1984, national computer conference and exposition

With recent advances in very large scale integrated circuit (VLSI) design, the once-distinct boundaries of micro-, mini-, and mainframe computer architectures are eroding. For example, the Motorola 68000, the Z8000 CPU, and the Intel 8086 have broken ...
Marvell inside

Look inside an e-reader, game console, Blu-ray player, TV, or smartphone and odds are you-ll find a cluster of chips designed by Marvell, a 15-year-old Silicon Valley firm. Marvell crafts the CPU as well as the wireless transmitters and receivers, the ...
An evaluation of speculative instruction execution on simultaneous multithreaded processors

Modern superscalar processors rely heavily on speculative execution for performance. For example, our measurements show that on a 6-issue superscalar, 93% of committed instructions for SPECINT95 are speculative. Without speculation, processor resources ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '03: Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

November 2003

899 pages

ISBN:1581137621

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society

United States

Publication History

Published: 09 November 2003

Check for updates

Qualifiers

Article

Conference

ICCAD03

Sponsor:

SIGDA

ICCAD03: The International Conference on Computer-Aided Design

November 9 - 13, 2003

Acceptance Rates

ICCAD '03 Paper Acceptance Rate 129 of 490 submissions, 26%;

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

10
Total Citations
View Citations
269
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 25 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Galuzzi CBertels K(2011)The Instruction-Set Extension ProblemACM Transactions on Reconfigurable Technology and Systems10.1145/1968502.19685094:2(1-28)Online publication date: 1-May-2011
https://dl.acm.org/doi/10.1145/1968502.1968509
Bordoloi UHuynh HChakraborty SMitra T(2009)Evaluating design trade-offs in customizable processorsProceedings of the 46th Annual Design Automation Conference10.1145/1629911.1629978(244-249)Online publication date: 26-Jul-2009
https://dl.acm.org/doi/10.1145/1629911.1629978
Galanis MDimitroulakos GTragoudas SGoutis C(2008)Speedups in embedded systems with a high-performance coprocessor datapathACM Transactions on Design Automation of Electronic Systems10.1145/1255456.125547212:3(1-22)Online publication date: 22-May-2008
https://dl.acm.org/doi/10.1145/1255456.1255472
Huynh HSim JMitra TKim TSainrat PLumetta SNavarro N(2007)An efficient framework for dynamic reconfiguration of instruction-set customizationProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289906(135-144)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289881.1289906
Galanis MDimitroulakos GGoutis CZhou HMacii EYan ZMassoud Y(2007)Improving performance and energy consumption in embedded microprocessor platforms with a flexible custom coprocessor data-pathProceedings of the 17th ACM Great Lakes symposium on VLSI10.1145/1228784.1228792(2-7)Online publication date: 11-Mar-2007
https://dl.acm.org/doi/10.1145/1228784.1228792
Galanis MDimitroulakos GGoutis C(2006)Performance improvements of microprocessor platforms with a coarse-grained reconfigurable data-pathProceedings of the 10th WSEAS international conference on Systems10.5555/1984211.1984256(232-237)Online publication date: 10-Jul-2006
https://dl.acm.org/doi/10.5555/1984211.1984256
Cheung NParameswaran SHenkel JTang T(2005)Battery-aware instruction generation for embedded processorsProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120960(553-556)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120960
Shee SParameswaran SCheung NEles PJantsch ABergamaschi R(2005)Novel architecture for loop accelerationProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1084834.1084908(297-302)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1145/1084834.1084908
Yu PMitra TEles PJantsch ABergamaschi R(2005)Satisfying real-time constraints with custom instructionsProceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/1084834.1084879(166-171)Online publication date: 19-Sep-2005
https://dl.acm.org/doi/10.1145/1084834.1084879
Brisk PKaplan ASarrafzadeh MMalik SFix LKahng A(2004)Area-efficient instruction set synthesis for reconfigurable system-on-chip designsProceedings of the 41st annual Design Automation Conference10.1145/996566.996679(395-400)Online publication date: 7-Jun-2004
https://dl.acm.org/doi/10.1145/996566.996679

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten