research-article

The Instruction-Set Extension Problem: A Survey

Authors:

Koen BertelsAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 4, Issue 2

Article No.: 18, Pages 1 - 28

https://doi.org/10.1145/1968502.1968509

Published: 01 May 2011 Publication History

Abstract

The extension of a given instruction-set with specialized instructions has become a common technique used to speed up the execution of applications. By identifying computationally intensive portions of an application to be partitioned in segments of code to execute in software and segments of code to execute in hardware, the execution of an application can be considerably speeded up. Each segment of code implemented in hardware can then be seen as a specialized application-specific instruction extending a given instruction-set. Although a number of approaches exist in literature proposing different methodologies to customize an instruction-set, the description of the problem consists only of sporadic comparisons limited to isolated problems. This survey presents a unique detailed description of the problem and provides an exhaustive overview of the research in the past years in instruction-set extension. This article presents a thorough analysis of the issues involved during the customization of an instruction-set by means of a set of specialized application-specific instructions. The investigation of the problem covers both instruction generation and instruction selection and different kinds of customizations are analyzed in a great detail.

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Henriques MBispo JPaulino N(2024)Using Source-to-Source to Target RISC-V Custom Extensions: UVE Case-StudyProceedings of the 16th Workshop on Rapid Simulation and Performance Evaluation for Design10.1145/3642921.3642930(42-50)Online publication date: 18-Jan-2024
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Hussein EWaschneck BMayr C(2024)Automating application-driven customization of ASIPsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103080148:COnline publication date: 1-Mar-2024
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Index Terms

The Instruction-Set Extension Problem: A Survey
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing

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cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 4, Issue 2

May 2011

216 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/1968502

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Publication History

Published: 01 May 2011

Accepted: 01 January 2010

Revised: 01 September 2009

Received: 01 May 2008

Published in TRETS Volume 4, Issue 2

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https://dl.acm.org/doi/10.1145/3642921.3642930
Hussein EWaschneck BMayr C(2024)Automating application-driven customization of ASIPsJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2024.103080148:COnline publication date: 1-Mar-2024
https://dl.acm.org/doi/10.1016/j.sysarc.2024.103080
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https://doi.org/10.1541/ieejias.143.94
Ganon OLevi I(2023)Modular Processor Architecture with Cryptography ISA Extensions2023 21st IEEE Interregional NEWCAS Conference (NEWCAS)10.1109/NEWCAS57931.2023.10198046(1-2)Online publication date: 26-Jun-2023
https://doi.org/10.1109/NEWCAS57931.2023.10198046
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Funck MHerdt VDrechsler R(2022)Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions2022 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS54261.2022.9770108(14-19)Online publication date: 6-Apr-2022
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Paulino NBispo JFerreira JCardoso J(2021)A Binary Translation Framework for Automated Hardware GenerationIEEE Micro10.1109/MM.2021.308867041:4(15-23)Online publication date: 1-Jul-2021
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Marshall BPage DHung Pham T(2021)A lightweight ISE for ChaCha on RISC-V2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP52443.2021.00011(25-32)Online publication date: Jul-2021
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Jakobs MPauck FPlatzner MWehrheim HWiersema T(2021)Software/Hardware Co-Verification for Custom Instruction Set ProcessorsIEEE Access10.1109/ACCESS.2021.31312139(160559-160579)Online publication date: 2021
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Bruns NGroße DDrechsler RMohsenin TZhao WChen YMutlu O(2020)Early Verification of ISA Extension Specifications using Deep Reinforcement LearningProceedings of the 2020 on Great Lakes Symposium on VLSI10.1145/3386263.3406901(297-302)Online publication date: 7-Sep-2020
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