research-article

A Synthesis Algorithm for Reconfigurable Interconnection Networks

Authors:

Insup Lee,

David SmitleyAuthors Info & Claims

IEEE Transactions on Computers, Volume 37, Issue 6

Pages 691 - 699

https://doi.org/10.1109/12.2207

Published: 01 June 1988 Publication History

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Abstract

The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average-case performance prediction and confirm that, on the average, the optimum topologies are generated.

References

[1]

{1} L. Wittie, "Communication structures for large networks of microcomputers," IEEE Trans. Comput., vol. C-30, pp. 264-273, Apr. 1981.

Google Scholar

[2]

{2} D. P. Agrawal and V. K. Janakiram, "Evaluating the performance of multicomputer configurations," Computer, vol. 19, pp. 23-37, May 1986.

Digital Library

Google Scholar

[3]

{3} A. L. Rosenberg, "Data encodings and their costs," Acta Informatica , vol. 9, pp. 273-292, 1978.

Digital Library

Google Scholar

[4]

{4} H. Li, C. Wang, and M. Lavin, "The V language for polymorphic architectures and algorithms," in Intermediate-Level Image Processing , M. B. Duff, Ed. New York: Academic, 1986.

Google Scholar

[5]

{5} K. E. Batcher, "Design of a massively parallel processor," IEEE Trans. Comput., pp. 836-840, Sept. 1980.

Digital Library

Google Scholar

[6]

{6} L. Snyder, "Introduction to the configurable, highly parallel computer," Computer, vol. 15, pp. 47-56, Jan. 1982.

Digital Library

Google Scholar

[7]

{7} D. Smitley, I. Lee, and S. Goldwasser, "The design of an optical network and its utilization," in Proc. 1986 Optoelectron. Laser Appl. Sci. Eng. Conf., Los Angeles, CA, Jan. 1986.

Google Scholar

[8]

{8} A. A. Sawchuk, B. K. Jenkins, C. S. Raghavendra, and A. Varma, "Optical interconnection networks," in Proc. 1985 Int. Conf. Parallel Processing, Aug. 1985, pp. 388-392.

Google Scholar

[9]

{9} S. Bokhari, "On the mapping problem," IEEE Trans. Comput., vol. C-30, pp. 207-214, Mar. 1981.

Google Scholar

[10]

{10} F. Haray, Graph Theory. Reading, MA: Addison-Wesley, 1969.

Google Scholar

[11]

{11} M. Yannakakis, "Edge deletion problems," SIAM J. Comput., vol. 10, pp. 297-309, May 1981.

Crossref

Google Scholar

[12]

{12} M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. San Francisco, CA: Freeman, 1979.

Digital Library

Google Scholar

[13]

{13} I. Lee and D. Smitley, "A synthesis algorithm for reconfigurable interconnection networks," Tech. Rep., MS-CIS-86-46, Dep. Comput. Inform. Sci., Univ. Pennsylvania, May 1986.

Google Scholar

[14]

{14} J. Edmonds and E. L. Johnson, "Matching: A well-solved class of integer linear programs," in Combinatorical Structures Appl., Proc. Calgary Int. Conf. Comb. Struct. Appl., New York: Gordon and Breach, June 1969, pp. 89-92.

Google Scholar

[15]

{15} C. Berge, "Alternating chain methods: A survey," in Graph Theory and Computing, R. C. Read, Ed. New York: Academic, 1972.

Google Scholar

[16]

{16} H. N. Gabow, "An efficient reduction technique for degree-constrained subgraph and bidirected network flow problems," in Proc. 1983 ACM Symp. Theory Comput., 1983, pp. 448-456.

Crossref

Google Scholar

[17]

{17} A. V. Aho, J. E. Hopcroft, and J. D. Ullman, The Design and Analysis of Computer Algorithms. Reading, MA: Addison-Wesley, 1974.

Digital Library

Google Scholar

[18]

{18} B. Bollobas and S. E. Eldridge, "Maximal matchings in graphs with given minimal and maximal degrees," in Proc. Cambridge Phil. Soc., vol. 79, 1974, pp. 221-234.

Crossref

Google Scholar

[19]

{19} M. Kano and A. Saito, "{a, b}-factors of graphs," Discrete Math., vol. 47, pp. 113-116, 1983.

Digital Library

Google Scholar

[20]

{20} B. Bollobas, Graph Theory, An Introductory Course. New York: Springer-Verlag, 1979.

Google Scholar

[21]

{21} E. Shamir and E. Upfal, "On factors in random graphs," Israel J. Math., vol. 39, pp. 297-302, 1981.

Crossref

Google Scholar

[22]

{22} N. C. Wormald, "The asymptotic connectivity of labelled regular graphs," J. Combinatorial Theory Series B 31, pp. 156-167, 1981.

Crossref

Google Scholar

Cited By

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Baba TYoshinaga TIijima TIwamoto YHamada MSuzuki MPryor DMontry GMartin J(1990)A parallel object-oriented total architectureProceedings of the 1990 ACM/IEEE conference on Supercomputing10.5555/110382.110445(276-285)Online publication date: 12-Nov-1990
https://dl.acm.org/doi/10.5555/110382.110445
Murakami KMori SFukuda ASueyoshi TTomita SPaul GPapatheodorou TGannon DPudue E(1989)The Kyushu University reconfigurable parallel processorProceedings of the 3rd international conference on Supercomputing10.1145/318789.318828(351-360)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/318789.318828
Murakami KFukuda ASueyoshi TTomita S(1988)An overview of the Kyushu University reconfigurable parallel processorACM SIGARCH Computer Architecture News10.1145/54331.5434116:4(130-137)Online publication date: 1-Sep-1988
https://dl.acm.org/doi/10.1145/54331.54341

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A Synthesis Algorithm for Reconfigurable Interconnection Networks

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Reviews

Reviewer: Norman Stanley Scott

The performance of a parallel algorithm depends in part on how well its communication characteristics match the interconnection topology of the parallel system on which it is executing—different algorithms exhibit different communication patterns. General-purpose parallel systems that employ interconnection networks are unable to fully exploit the efficiency of the algorithms they are executing. It is therefore desirable for a parallel system to use a topology that can be configured to match the communication characteristics of the algorithm. This paper assumes an r-configurable network, i.e., a network that can be configured into any topology in which the number of communication links is at most some constant r. The paper describes a suboptimal synthesis algorithm that takes as input the constant r and a task graph representing the algorithm to be executed. The nodes of the task group correspond to individual tasks, and the edges signify communication between two tasks. The output of the algorithm is an r-degree constrained connected graph representing a network topology that closely matches the communication requirements of the algorithm. The synthesis algorithm is proved to have a time complexity of O( n &vbm0; E( G) &vbm0; ), where n is the number of nodes and E( G) is the edge set of the task graph. The best, worst, and average cardinalities of the topologies produced by the synthesis algorithm are comprehensively analyzed. This paper tackles an important problem and is intended for a research audience. It is thorough, well written, and supported by helpful references.

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cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 37, Issue 6

June 1988

136 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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IEEE Computer Society

United States

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Published: 01 June 1988

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Baba TYoshinaga TIijima TIwamoto YHamada MSuzuki MPryor DMontry GMartin J(1990)A parallel object-oriented total architectureProceedings of the 1990 ACM/IEEE conference on Supercomputing10.5555/110382.110445(276-285)Online publication date: 12-Nov-1990
https://dl.acm.org/doi/10.5555/110382.110445
Murakami KMori SFukuda ASueyoshi TTomita SPaul GPapatheodorou TGannon DPudue E(1989)The Kyushu University reconfigurable parallel processorProceedings of the 3rd international conference on Supercomputing10.1145/318789.318828(351-360)Online publication date: 1-Jun-1989
https://dl.acm.org/doi/10.1145/318789.318828
Murakami KFukuda ASueyoshi TTomita S(1988)An overview of the Kyushu University reconfigurable parallel processorACM SIGARCH Computer Architecture News10.1145/54331.5434116:4(130-137)Online publication date: 1-Sep-1988
https://dl.acm.org/doi/10.1145/54331.54341

Abstract

References

Cited By

Index Terms

Recommendations

PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness

The Performance of Multistage Interconnection Networks for Multiprocessors

Creating Disjoint Paths in Gamma Interconnection Networks

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