research-article

On Error Injection for NoC Platforms: A UVM-based Practical Case Study

Authors:

Sameh El-Ashry,

Moamen A. Ibrahem,

Mostafa Khamis,

Mohamed AbdElsalam,

M. Watheq El-KharashiAuthors Info & Claims

NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures

Article No.: 2, Pages 1 - 6

https://doi.org/10.1145/3139540.3139544

Published: 14 October 2017 Publication History

Abstract

Error injection has become critically important for testing the reliability of the hardware of any system. Measuring how a design under test reacts to different error injection methodologies is very essential for verification engineers to design dependable Universal Verification Methodology (UVM) scoreboards for error-detection purposes. The main target of this paper is to decide on the feasibility and compatibility of some error injection techniques when used with Networks-on-Chip (NoC) platforms. We target a UVM-based error injection and detection environment with its reusable components. Proposed techniques, introducing both positive and negative test scenarios, are applied to two example NoC components: a base router, which is a simple case study to prove proposed schemes and a configurable router, which is a complex open-source case study that provides the ability of changing the router's architecture with the change of some parameters and applied algorithms. The main novelty of our work is to integrate a full UVM environment with the various approaches of error injection and detection using reusable, generic UVM environment and components for NoC while inspecting network response according to error type and injection methodology.

References

[1]

H. Elmiligi, A. A. Morgan, M.W. El-Kharashi, and F. Gebali, "A topology-based design methodology for networks-on-chip applications," in Proceedings of the Second IEEE International Design and Test Workshop (IDT 2007), Cairo, Egypt, Dec. 16-18, 2007, pp. 61--65.

[2]

H. Elmiligi, A. A. Morgan, M. W. El-Kharashi, and F. Gebali, "A reliability-aware design methodology for networks-on-chip applications," in Proceedings of the 2009 Fourth IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS'09), Cairo, Egypt, Apr. 6-7, 2009, pp. 107--112.

[3]

H. Elmiligi, A. A. Morgan, M. W. El-Kharashi, and F. Gebali, "Networks-on-chip topology optimization subject to power, delay, and reliability constraints," in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, May 30-Jun. 2, 2010, pp. 2354--2357.

[4]

W. J. Dally and B. P. Towles, Principles and Practices of Interconnection Networks. Elsevier, Inc., 2004.

Digital Library

[5]

M. Sallam, M. W. El-Kharashi, and M. Dessouky, "The connection-then-credit flow control protocol for networks-on-chips: Implementation trade-offs," in Proceedings of the Seventh International Workshop on Network on Chip Architectures (NoCArc 2014), held in conjunction with the 47th Annual IEEE/ACM International Symposium on Microarcchitectures (MICRO-47), Cambridge, UK, Dec. 13, 2014, pp. 25--30.

Digital Library

[6]

P Oury, N Heaton, and S Penman, "Methodology to verify, debug and evaluate performances of NoC based interconnects" in Proceedings of the 8th International Workshop on Network on Chip Architectures (NoCArc 2015), held in conjunction with the 48th Annual IEEE/ACM International Symposium on Microarcchitectures (MICRO-48), Waikiki, HI, USA, Dec. 05, 2015, pp. 39--42.

[7]

A. A. Morgan, H. Elmiligi, M. W. El-Kharashi, and F. Gebali, "Multi-objective optimization for networks-on-chip architectures using genetic algorithms," in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, May 30-Jun. 2, 2010, pp. 3725--3728.

[8]

Accellera, Universal Verification Methodology (UVM) 1.0 User's Guide, 2011.

[9]

G. Micheli and L. Benini, Networks on Chips -- Technology and Tools, Morgan Kaufmann Publishers 2006.

[10]

B. Wang, J. Xie, and Q. Wang, "Crosstalk-aware channel transmitting scheme for error resilience NoC interconnects," in Proceedings of Electronics, Communications and Control (ICECC), 2011, pp. 190--193.

[11]

E. K. Gawish, M. W. El-Kharashi, M. F. Abu-Elyazeed, "Variability-tolerant NoC link design", in Proceedings of the Fifth International Workshop on Network on Chip Architectures (NoCArc'2012), held in conjunction with the 45th Annual IEEE/ACM International Symposium on Microarchitectures, Vancouver, BC, Canada, 2012, pp. 57--62.

Digital Library

[12]

A. Berman, and I. Keidar, "Low overhead error detection for Networks-on-Chip", in Proceedings of International Conference on Computer Design (ICCD), 2009, pp. 219--225.

[13]

D. Steinberg, "Constrained random error injection for functional verification", US Patent NO. 8,595,680, 2013.

[14]

Y. Y. Chen and G. E. Jan, "Development of scenario-based fault injection platform and its application study", Tamkang Journal of Science and Engineering, Vol. 13, No. 2, 2010, pp. 205--214.

[15]

B. Ustaoglu and B. Ors, "Design and implementation of a custom verification environment for fault injection and analysis on an embedded microprocessor", Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE), 2015.

[16]

H. Ziade, "A survey on fault injection techniques", The International Arab Journal of Information Technology (IAJIT), vol. 1, no. 2, 2004, pp. 171--186.

[17]

H. V. Schoot and A. Yehia, "UVM and Emulation: How to Get Your Ultimate Testbench Acceleration Speed-up" in Proceedings of Design and Verification Conference (DVCON), Munich, Germany, 2015.

[18]

J. Montesano, "UVM sequence item based error injection", SNUG Ottawa Synopsys Conference, 2012.

[19]

K. Schwartz, and T. Corcoran, "Error injection: when good input goes bad" in Proceedings of Design and Verification Conference (DVCON), USA, 2017.

[20]

M. S. Sayed, A. Shalaby, M. El-Sayed, and V. Goulart, "Flexible router architecture for network-on-chip", Computers & Mathematics with Applications, 64 (5), 1301--1310, 2012.

Digital Library

[21]

A. S. Eissa, M. A. Ibrahem, M. A. Elmohr, Y. Zamzam, A. El-Yamany, S. El-Ashry, M. Khamis, and A. Shalaby, "A reusable verification environment for NoC Platforms using UVM" in Proceedings of 17th IEEE International Conference on Smart Technologies (EUROCON), 2017.

[22]

D. U. Becker, N. Jiang, G. Michelogiannakis, and W. J. Dally, "Adaptive backpressure: Efficient buffer management for On-Chip Networks," in Proceedings of the 30th IEEE International Conference on Computer Design (ICCD), 2012, pp. 419--426.

Digital Library

[23]

A. El-Naggar, E. Massoud, A. Medhat, H. Ibrahim, B. Al-Abassy, S. El-Ashry, M. Khamis, and A. Shalaby, "A Narrative of UVM testbench environment for interconnection routers: A practical approach", in Proceedings of the 11th International Design & Test Symposium (IDT), 2016, pp. 98--103.

[24]

S. El-Ashry, K. Salah, "A Functional Coverage Approach for Direct Testing: An Industrial IP as a Case Study", in Proceedings of the 16th International Conference on Computer as a tool (EUROCON), Salamanca, Spain, 2015.

[25]

A. Meyer, H. Foster, "Metrics in SoC Verification: Not just for coverage anymore", in Proceedings of Design and Verification Conference (DVCON), San Jose, CA, 2013.

Cited By

Khamis MEl-Ashry SAbdElsalam MEl-Kharashi MShalaby A(2022)Emulation and verification framework for MPSoC based on NoC and RISC-VDesign Automation for Embedded Systems10.1007/s10617-022-09265-126:3-4(133-159)Online publication date: 14-Sep-2022
https://dl.acm.org/doi/10.1007/s10617-022-09265-1
Qamar SButt WAnwar MAzam FKhan M(2020)A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design VerificationProceedings of the 2020 9th International Conference on Software and Computer Applications10.1145/3384544.3384547(339-343)Online publication date: 18-Feb-2020
https://dl.acm.org/doi/10.1145/3384544.3384547
El-Ashry SKhamis MIbrahim HShalaby AAbdelsalam MEl-Kharashi M(2020)On Error Injection for NoC Platforms: A UVM-Based Generic Verification EnvironmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290892139:5(1137-1150)Online publication date: May-2020
https://doi.org/10.1109/TCAD.2019.2908921
Show More Cited By

Index Terms

On Error Injection for NoC Platforms: A UVM-based Practical Case Study
1. Networks
  1. Network types
    1. Network on chip

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cover image ACM Conferences

NoCArc '17: Proceedings of the 10th International Workshop on Network on Chip Architectures

October 2017

63 pages

ISBN:9781450355421

DOI:10.1145/3139540

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 14 October 2017

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MICRO-50

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SIGMICRO

MICRO-50: The 50th Annual IEEE/ACM International Symposium on Microarchitecture

October 14, 2017

MA, Cambridge, USA

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NoCArc '17 Paper Acceptance Rate 6 of 20 submissions, 30%;

Overall Acceptance Rate 46 of 122 submissions, 38%

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Cited By

Khamis MEl-Ashry SAbdElsalam MEl-Kharashi MShalaby A(2022)Emulation and verification framework for MPSoC based on NoC and RISC-VDesign Automation for Embedded Systems10.1007/s10617-022-09265-126:3-4(133-159)Online publication date: 14-Sep-2022
https://dl.acm.org/doi/10.1007/s10617-022-09265-1
Qamar SButt WAnwar MAzam FKhan M(2020)A Comprehensive Investigation of Universal Verification Methodology (UVM) Standard for Design VerificationProceedings of the 2020 9th International Conference on Software and Computer Applications10.1145/3384544.3384547(339-343)Online publication date: 18-Feb-2020
https://dl.acm.org/doi/10.1145/3384544.3384547
El-Ashry SKhamis MIbrahim HShalaby AAbdelsalam MEl-Kharashi M(2020)On Error Injection for NoC Platforms: A UVM-Based Generic Verification EnvironmentIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.290892139:5(1137-1150)Online publication date: May-2020
https://doi.org/10.1109/TCAD.2019.2908921
Danilov IKhazanova ABalbekov AGorbunov M(2019)Standard Verification Flow Compatible Layout-Aware Fault Injection Technique for Single Event Effects Tolerant ASIC Design2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS)10.1109/RADECS47380.2019.9745679(1-5)Online publication date: Sep-2019
https://doi.org/10.1109/RADECS47380.2019.9745679
Khamis MEl-Ashry SShalaby AAbdElsalam MEl-Kharashi M(2018)A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation2018 11th International Workshop on Network on Chip Architectures (NoCArc)10.1109/NOCARC.2018.8541158(1-6)Online publication date: Oct-2018
https://doi.org/10.1109/NOCARC.2018.8541158
El-Ashry SAdel A(2018)Efficient Methodology of Sampling UVM RAL During Simulation for SoC Functional Coverage2018 19th International Workshop on Microprocessor and SOC Test and Verification (MTV)10.1109/MTV.2018.00022(61-66)Online publication date: Dec-2018
https://doi.org/10.1109/MTV.2018.00022

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