Resource allocation in a high clock rate microprocessor
Pages 98 - 109
Abstract
This paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is used to estimate the resources required to build processors with varying sizes of on-chip memories, in both single and dual issue models. Recommendations are then made to increase the effectiveness of each of the models.
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- Resource allocation in a high clock rate microprocessor
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Resource allocation in a high clock rate microprocessor
ASPLOS VI: Proceedings of the sixth international conference on Architectural support for programming languages and operating systemsThis paper discusses the design of a high clock rate (300MHz) processor. The architecture is described, and the goals for the design are explained. The performance of three processor models is evaluated using trace-driven simulation. A cost model is ...
The MIPS R10000 Superscalar Microprocessor
The Mips R10000 is a dynamic superscalar microprocessor that implements the 64-bit Mips-4 Instruction Set Architecture. It fetches and decodes four instructions per cycle and dynamically issues them to five fully pipelined low-latency execution units. ...
A complexity-effective microprocessor design with decoupled dispatch queues and prefetching
Continuing demands for high degrees of Instruction Level Parallelism (ILP) require large dispatch queues (or centralized reservation stations) in modern superscalar microprocessors. However, such large dispatch queues are inevitably accompanied by high ...
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Publication History
Published: 01 November 1994
Published in SIGOPS Volume 28, Issue 5
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