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Bytecode fetch optimization for a Java interpreter

Published: 01 October 2002 Publication History

Abstract

Interpreters play an important role in many languages, and their performance is critical particularly for the popular language Java. The performance of the interpreter is important even for high-performance virtual machines that employ just-in-time compiler technology, because there are advantages in delaying the start of compilation and in reducing the number of the target methods to be compiled. Many techniques have been proposed to improve the performance of various interpreters, but none of them has fully addressed the issues of minimizing redundant memory accesses and the overhead of indirect branches inherent to interpreters running on superscalar processors. These issues are especially serious for Java because each bytecode is typically one or a few bytes long and the execution routine for each bytecode is also short due to the low-level, stack-based semantics of Java bytecode. In this paper, we describe three novel techniques of our Java bytecode interpreter, write-through top-of-stack caching (WT), position-based handler customization (PHC), and position-based speculative decoding (PSD), which ameliorate these problems for the PowerPC processors. We show how each technique contributes to improving the overall performance of the interpreter for major Java benchmark programs on an IBM POWER3 processor. Among three, PHC is the most effective one. We also show that the main source of memory accesses is due to bytecode fetches and that PHC successfully eliminates the majority of them, while it keeps the instruction cache miss ratios small.

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  • (2022)A fast in-place interpreter for WebAssemblyProceedings of the ACM on Programming Languages10.1145/35633116:OOPSLA2(646-672)Online publication date: 31-Oct-2022
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    Published In

    cover image ACM Conferences
    ASPLOS X: Proceedings of the 10th international conference on Architectural support for programming languages and operating systems
    October 2002
    318 pages
    ISBN:1581135742
    DOI:10.1145/605397
    • cover image ACM SIGARCH Computer Architecture News
      ACM SIGARCH Computer Architecture News  Volume 30, Issue 5
      Special Issue: Proceedings of the 10th annual conference on Architectural Support for Programming Languages and Operating Systems
      December 2002
      296 pages
      ISSN:0163-5964
      DOI:10.1145/635506
      Issue’s Table of Contents
    • cover image ACM SIGOPS Operating Systems Review
      ACM SIGOPS Operating Systems Review  Volume 36, Issue 5
      December 2002
      296 pages
      ISSN:0163-5980
      DOI:10.1145/635508
      Issue’s Table of Contents
    • cover image ACM SIGPLAN Notices
      ACM SIGPLAN Notices  Volume 37, Issue 10
      October 2002
      296 pages
      ISSN:0362-1340
      EISSN:1558-1160
      DOI:10.1145/605432
      Issue’s Table of Contents
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    Published: 01 October 2002

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    Author Tags

    1. Java
    2. PowerPC
    3. bytecode interpreter
    4. performance
    5. pipelined interpreter
    6. stack caching
    7. superscalar processor

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    Cited By

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    • (2022)A fast in-place interpreter for WebAssemblyProceedings of the ACM on Programming Languages10.1145/35633116:OOPSLA2(646-672)Online publication date: 31-Oct-2022
    • (2008)Optimization strategies for a java virtual machine interpreter on the cell broadband engineProceedings of the 5th conference on Computing frontiers10.1145/1366230.1366265(189-198)Online publication date: 5-May-2008
    • (2005)High performance annotation-aware JVM for Java cardsProceedings of the 5th ACM international conference on Embedded software10.1145/1086228.1086240(52-61)Online publication date: 18-Sep-2005
    • (2004)Code sharing among states for stack-caching interpreterProceedings of the 2004 workshop on Interpreters, virtual machines and emulators10.1145/1059579.1059584(15-22)Online publication date: 7-Jun-2004
    • (2004)Combining stack caching with dynamic superinstructionsProceedings of the 2004 workshop on Interpreters, virtual machines and emulators10.1145/1059579.1059583(7-14)Online publication date: 7-Jun-2004
    • (2004)Partial redundancy elimination for access expressions by speculative code motionSoftware—Practice & Experience10.1002/spe.60434:11(1065-1090)Online publication date: 1-Sep-2004
    • (2022)RegCPython: A Register-based Python Interpreter for Better PerformanceACM Transactions on Architecture and Code Optimization10.1145/356897320:1(1-25)Online publication date: 21-Oct-2022

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