research-article

Fast buffering for optimizing worst slack and resource consumption in repeater trees

Authors:

Christoph Bartoschek,

Dieter Rautenbach,

Jens VygenAuthors Info & Claims

ISPD '09: Proceedings of the 2009 international symposium on Physical design

Pages 43 - 50

https://doi.org/10.1145/1514932.1514942

Published: 29 March 2009 Publication History

Abstract

We present a very fast algorithm for buffering repeater trees. We scan a given preliminary topology in a bottom-up fashion and insert buffers and inverters, respecting the parities of the sinks. Information obtained by preprocessing allows for very fast decisions. To bound the number of shielding repeaters, they are only used where necessary to maximize the worst slack. Furthermore, instead of using a fixed set of repeater positions, they are computed on the fly based on the already buffered subtrees. Another key feature of our algorithm is that we modify the preliminary topology while buffering in order to avoid parallel wires or too many inverters.

Experimental results on industrial designs illustrate the speed, quality, practicality, and flexibility of our procedure. In particular, we buffer about 100,000 repeater trees per minute and obtain results that are close to the theoretical optimum in several respects.

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Cited By

Daboul SHeld SNatura BRotter D(2023)Global Interconnect OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/358704428:5(1-24)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3587044
Brenner USilvanus A(2023)BonnLogic: Delay optimization by And-Or Path restructuringIntegration10.1016/j.vlsi.2022.11.01489(123-133)Online publication date: Mar-2023
https://doi.org/10.1016/j.vlsi.2022.11.014
Brenner USilvanus AWang T(2022)Delay Optimization of Combinational Logic by AND-OR Path RestructuringProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712548(403-409)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712548
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Index Terms

Fast buffering for optimizing worst slack and resource consumption in repeater trees

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Published In

cover image ACM Conferences

ISPD '09: Proceedings of the 2009 international symposium on Physical design

March 2009

208 pages

ISBN:9781605584492

DOI:10.1145/1514932

General Chair:
Gi-Joon Nam
IBM Research
,
Program Chair:
Prashant Saxena
Synopsys

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 29 March 2009

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March 29 - April 1, 2009

California, San Diego, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Daboul SHeld SNatura BRotter D(2023)Global Interconnect OptimizationACM Transactions on Design Automation of Electronic Systems10.1145/358704428:5(1-24)Online publication date: 9-Sep-2023
https://dl.acm.org/doi/10.1145/3587044
Brenner USilvanus A(2023)BonnLogic: Delay optimization by And-Or Path restructuringIntegration10.1016/j.vlsi.2022.11.01489(123-133)Online publication date: Mar-2023
https://doi.org/10.1016/j.vlsi.2022.11.014
Brenner USilvanus AWang T(2022)Delay Optimization of Combinational Logic by AND-OR Path RestructuringProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712548(403-409)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712548
Daboul SHeld SNatura BRotter D(2019)Global Interconnect Optimization2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD45719.2019.8942155(1-8)Online publication date: Nov-2019
https://doi.org/10.1109/ICCAD45719.2019.8942155
Bartoschek CHeld SMaíberg JRautenbach DVygen J(2010)The repeater tree construction problemInformation Processing Letters10.1016/j.ipl.2010.08.016110:24(1079-1083)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1016/j.ipl.2010.08.016
Maßberg JRautenbach D(2009)Binary trees with choosable edge lengthsInformation Processing Letters10.1016/j.ipl.2009.07.002109:18(1087-1092)Online publication date: 1-Aug-2009
https://dl.acm.org/doi/10.1016/j.ipl.2009.07.002

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