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Circuit partitioning for efficient logic BIST synthesis

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A. Irion,

G. Kiefer,

H. Vranken,

H. WunderlichAuthors Info & Claims

DATE '01: Proceedings of the conference on Design, automation and test in Europe

Pages 86 - 91

Published: 13 March 2001 Publication History

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References

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Wohl PWaicukauski JPatel SAmin MGetreu IFix LLavagno L(2003)Efficient compression and application of deterministic patterns in a logic BIST architectureProceedings of the 40th annual Design Automation Conference10.1145/775832.775976(566-569)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775976

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Circuit partitioning for efficient logic BIST synthesis

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ICCAD '97: Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

Cycle simulation techniques, such as levelized compiled code, can ordinarily be applied only to synchronous designs. They usually cannot be applied to designs containing circuit features like combinational paths, multiple clock domains, generated clocks,...

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DATE '01: Proceedings of the conference on Design, automation and test in Europe

March 2001

756 pages

ISBN:0769509932

Editors:
Wolfgang Nebel
Oldenburg Univ. and OFFIS, Germany
,
Ahmed Jerraya
TIMA, Grenoble, France

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IEEE Press

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Published: 13 March 2001

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DATE01: Design, Automation and Test in Europe

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Wohl PWaicukauski JPatel SAmin MGetreu IFix LLavagno L(2003)Efficient compression and application of deterministic patterns in a logic BIST architectureProceedings of the 40th annual Design Automation Conference10.1145/775832.775976(566-569)Online publication date: 2-Jun-2003
https://dl.acm.org/doi/10.1145/775832.775976

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Reconvergence-based circuit partitioning technique for combinational and sequential logic synthesis

A Reconvergence-Based Circuit Partitioning Technique for Combinational and Sequential Logic Synthesis

Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits

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Reconvergence-based circuit partitioning technique for combinational and sequential logic synthesis

A Reconvergence-Based Circuit Partitioning Technique for Combinational and Sequential Logic Synthesis

Efficient circuit partitioning to extend cycle simulation beyond synchronous circuits

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