Cited By
View all- Hamandawana PCho DChung T(2024)Speed-Dedup: A New Deduplication Framework for Enhanced Performance and Reduced Overhead in Scale-Out StorageElectronics10.3390/electronics1322439313:22(4393)Online publication date: 9-Nov-2024
FSDedup: Feature-Aware and Selective Deduplication for Improving Performance of Encrypted Non-Volatile Main Memory
Authors: 
Chunfeng Du, Zihang Lin, Suzhen Wu, Yifei Chen, Jiapeng Wu, Shengzhe Wang, Weichun Wang, Qingfeng Wu, Bo MaoAuthors Info & Claims
Chunfeng Du, Zihang Lin, Suzhen Wu, Yifei Chen, Jiapeng Wu, Shengzhe Wang, Weichun Wang, Qingfeng Wu, Bo MaoAuthors Info & ClaimsArticle No.: 22, Pages 1 - 33
Abstract
Enhancing the endurance, performance, and energy efficiency of encrypted Non-Volatile Main Memory (NVMM) can be achieved by minimizing written data through inline deduplication. However, existing approaches applying inline deduplication to encrypted NVMM suffer from substantial performance degradation due to high computing, memory footprint, and index-lookup overhead to generate, store, and query the cryptographic hash (fingerprint). In the preliminary ESD [14], we proposed the Error Correcting Code (ECC) assisted selective deduplication scheme, utilizing the ECC information as a fingerprint to identify similar data effectively and then leveraging the selective deduplication technique to eliminate a large amount of redundant data with high reference counts. In this article, we proposed FSDedup. Compared with ESD, FSDedup could leverage the prefetch cache to reduce the read overhead during similarity comparison and utilize the cache refresh mechanism to identify further and eliminate more redundant data. Extensive experimental evaluations demonstrate that FSDedup can enhance the performance of the NVMM system further than the ESD. Experimental results show that FSDedup can improve both write and read speed by up to 1.8×, enhance Instructions Per Cycle by up to 1.5×, and reduce energy consumption by up to 2.0×, compared to ESD.
References
[1]
2023. Memcached. Retrieved from https://memcached.org/
[2]
Irina Alam, Clayton Schoeny, Lara Dolecek, and Puneet Gupta. 2018. Parity++: Lightweight error correction for last level caches. In Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSNW’18).
[3]
AMD EPYC Processors. 2021. Retrieved from https://www.amd.com/zh-hans/processors/epyc-server-cpu-family
[4]
Amro Awad, Pratyusa Manadhata, Stuart Haber, Yan Solihin, and William Horne. 2016. Silent shredder: Zero-cost shredding for secure non-volatile main memory controllers. In Proceedings of the 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’16).
[5]
Amro Awad, Mao Ye, Yan Solihin, Laurent Njilla, and Kazi Zubair. 2019. Triad-nvm: Persistency for integrity-protected and encrypted non-volatile memories. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19).
[6]
Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, D. Hill, and A Wood. 2011. The Gem5 simulator. ACM SIGARCH Comput. Arch. News 39, 2 (May2011), 1–7.
[7]
James Bucek, Klaus Lange, and Jakim Kistowski. 2018. SPEC CPU2017: Next-generation compute benchmark. In Proceedings of the 9th ACM/SPEC International Conference on Performance Engineering (ICPE’18).
[8]
Ricardo Chaves, Leonel Sousa, Nicolas Sklavos, Apostolos Fournaris, Georgina Kalogeridou, Paris Kitsos, and Farhana Sheikh. 2016. Secure hashing: SHA-1, SHA-2, and SHA-3. In Circuits and Systems for Security and Privacy, 105–132.
[9]
Feng Chen, Tian Luo, and Xiaodong Zhang. 2011. CAFTL: A content-aware flash translation layer enhancing the lifespan of flash memory based solid state drives. In Proceedings of the 9th USENIX Conference on File and Stroage Technologies (FAST’11).
[10]
Zhengguo Chen, Youtao Zhang, and Nong Xiao. 2020. ExtraCC: Improving performance of secure NVM with extra counters and ECC. In Proceedings of the 36th International Conference on Massive Storage Systems and Technology (MSST’20).
[11]
Sangyeun Cho and Hyunjin Lee. 2009. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’09).
[12]
Brian F Cooper, Adam Silberstein, Erwin Tam, Raghu Ramakrishnan, and Russell Sears. 2010. Benchmarking cloud serving systems with YCSB. In Proceedings of the 1st ACM Symposium on Cloud Computing (SOCC’10).
[13]
Guzman De, B Larry, Ariel Sison, and Ruji Medina. 2018. MD5 secured cryptographic hash value. In Proceedings of the 2018 International Conference on Machine Learning and Machine Intelligence (MLMI’18).
[14]
Chunfeng Du, Suzhen Wu, Jiapeng Wu, Bo Mao, and Shengzhe Wang. 2023. ESD: An ECC-assisted and selective deduplication for encrypted non-volatile main memory. In Proceedings of the 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA’23).
[15]
ECC for L2 Cache Data Memory. 2022. Retrieved from https://www.intel.com/content/www/us/en/docs/programmable/683360/18-0/ecc-for-l2-cache-data-memory.html
[16]
Extended Asynchronous DRAM Refresh (eADR). 2021. Retrieved from https://www.intel.cn/content/www/cn/zh/products/docs/memory-storage/optane-persistent-memory/optane-persistent-memory-200-series-brief.html
[17]
Mark Gebhart, Joel Hestness, Ehsan Fatehi, Paul Gratz, and Stephen Keckler. 2009. Running PARSEC 2.1 on M5. Technical Report TR-09-32, The University of Texas at Austin, Department of Computer Science.
[18]
Roksana Hossain. 2019. Accelerating Sequence Calculations on Parallel GPU Architecture. Unpublished Ph.D. Dissertation, University of Calgary.
[19]
S. Ikeda, K. Miura, H. Yamamoto, K. Mizunuma, H. D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno. 2010. A perpendicular-anisotropy CoFeB–MgO magnetic tunnel junction. Nat. Mater. 9, 9 (Jul.2010), 721–724.
[20]
Intel Xeon Processor E5 Family. 2020. Retrieved from https://www.intel.com/content/www/us/en/processors/xeon/xeon-e5-family-spec-update.html
[21]
Luc Jaulmes, Miquel Moreto, Mateo Valero, and Marc Casas. 2019. A vulnerability factor for ECC-protected memory. In Proceedings of the 25th International Symposium on On-Line Testing and Robust System Design (IOLTS’19).
[22]
Benjamin Lee, Engin Ipek, Onur Mutlu, and Doug Burger. 2009. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09).
[23]
Sheng Li, Ho Ahn, Richard Strong, Jay Brockman, Dean Tullsen, and Norman Jouppi. 2009. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’09).
[24]
Sihang Liu, Aasheesh Kolli, Jinglei Ren, and Samira Khan. 2018. Crash consistency in encrypted non-volatile main memory systems. In Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA’18).
[25]
Bo Mao, Hong Jiang, Suzhen Wu, and Lei Tian. 2014. POD: Performance oriented I/O deduplication for primary storage systems in the cloud. In Proceedings of the 28th IEEE International Parallel and Distributed Processing Symposium (IPDPS’14).
[26]
Prashant Nair, DaeHyun Kim, and Moinuddin Qureshi. 2013. ArchShield: Architectural framework for assisting DRAM scaling by tolerating high error rates. In Proceedings of the 40th Annual International Symposium on Computer Architecture (ISCA’13).
[27]
Sungbo Park, Ingab Kang, Yaebin Moon, Jung Ho Ahn, and G Suh. 2021. BCD deduplication: Effective memory compression using partial cache-line deduplication. In Proceedings of the 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’21).
[28]
Minesh Patel, Jeremie Kim, Taha Shahroodi, Hasan Hassan, and Onur Mutlu. 2020. Bit-exact ecc recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics. In Proceedings of the 53rd International Symposium on Microarchitecture (MICRO’20).
[29]
Matthew Poremba, Tao Zhang, and Yuan Xie. 2015. NVMain 2.0: A user-friendly memory simulator to model non-volatile memory systems. IEEE Comput. Arch. Lett. 14, 2 (Feb.2015), 140–143.
[30]
Jiansheng Qiu, Yanqi Pan, Wen Xia, Xiaojia Huang, Wenjun Wu, Xiangyu Zou, Shiyi Li, and Yu Hua. 2023. Light-dedup: A light-weight inline deduplication framework for non-volatile memory file systems. In Proceedings of the 2023 USENIX Annual Technical Conference (ATC’23).
[31]
Qualcomm Centriq 2400 Processor. 2017. Retrieved from https://www.qualcomm.com/news/onq/2017/10/05/qualcomm-centriq-2400-designed-scalability-and-throughput-performance
[32]
Gururaj Saileshwar, Prashant Nair, Prakash Ramrakhyani, Wendy Elsasser, and Moinuddin Qureshi. 2018. Synergy: Rethinking secure-memory design for error-correcting memories. In Proceedings of the 24th IEEE International Symposium on High Performance Computer Architecture (HPCA’18).
[33]
Karan Shetti and Rajendra. 2014. Optimization and Scheduling of Applications in A Heterogeneous CPU-GPU Environment. Ph.D. Dissertation. Nanyang Technological University.
[34]
Kiran Srinivasan, Timothy Bisson, Garth Goodson, and Kaladhar Voruganti. 2012. iDedup: Latency-aware, inline data deduplication for primary storage. In Proceedings of the 10th USENIX Conference on File and Storage Technologies (FAST’12).
[35]
Shivam Swami, Joydeep Rakshit, and Kartik Mohanram. 2016. SECRET: Smartly encrypted energy efficient non-volatile memories. In Proceedings of the 53rd Design Automation Conference (DAC’16).
[36]
Chundong Wang, Qingsong Wei, Jun Yang, Cheng Chen, Yechao Yang, and Mingdi Xue. 2018. NV-dedup: High-performance inline deduplication for non-volatile memory. IEEE Trans. Comput. 67, 5 (May2018), 658–671.
[37]
Rujia Wang, Lei Jiang, Youtao Zhang, and Jun Yang. 2015. SD-PCM: Constructing reliable super dense phase change memory under write disturbance. In Proceedings of the 20th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’15).
[38]
Zixuan Wang, Xiao Liu, Jian Yang, Theodore Michailidis, Steven Swanson, and Jishen Zhao. 2020. Characterizing and modeling non-volatile memory systems. In Proceedings of the 53rd International Symposium on Microarchitecture (MICRO’20).
[39]
Benedikt Westermann, Danilo Gligoroski, and Svein Knapskog. 2010. Comparison of the power consumption of the 2nd round SHA-3 candidates. In Proceedings of the International Conference on ICT Innovations (ICCS’10).
[40]
Philip Wong, Heng Lee, Yu Shimeng, Chen YuSheng, Wu Yi, Chen Pang-Shiu, Lee Byoungil, Chen Frederick, and Tsai Ming-Jinn. 2012. Metal–oxide RRAM. Proc. IEEE 100, 6 (May2012), 1951–1970.
[41]
Suzhen Wu, Jiapeng Wu, Zhirong Shen, Zhihao Zhang, Zuocheng Wang, and Bo Mao. 2021. SimiEncode: A similarity-based encoding scheme to improve performance and lifetime of non-volatile main memory. In Proceedings of the 39th IEEE International Conference on Computer Design (ICCD’21).
[42]
Suzhen Wu, Jindong Zhou, Weidong Zhu, Hong Jiang, Zhijie Huang, Zhirong Shen, and Bo Mao. 2020. EaD: A collision-free and high performance deduplication scheme for flash storage systems. In Proceedings of the IEEE 38th International Conference on Computer Design (ICCD’20).
[43]
Wen Xia, Hong Jiang, Dan Feng, Lei Tian, Min Fu, and Zhongtao Wang. 2012. P-dedupe: Exploiting parallelism in data deduplication system. In Proceedings of the IEEE 7th International Conference on Networking, Architecture, and Storage (NAS’12).
[44]
Fan Yang, Youyou Lu, Youmin Chen, Haiyu Mao, and Jiwu Shu. 2019. No compromises: Secure NVM with crash consistency, write-efficiency and high-performance. In Proceedings of the 56th ACM/IEEE Design Automation Conference (DAC’19).
[45]
Jian Yang, Juno Kim, Morteza Hoseinzadeh, Joseph Izraelevitz, and Steve Swanson. 2020. An empirical guide to the behavior and use of scalable persistent memory. In Proceedings of the 18th USENIX Conference on File and Storage Technologies (FAST’20).
[46]
Zuoru Yang, Jingwei Li, and Patrick PC Lee. 2022. Secure and lightweight deduplicated storage via shielded deduplication-before-encryption. In Proceedings of the USENIX Annual Technical Conference (ATC’22). 37–52.
[47]
Mao Ye, Clayton Hughes, and Amro Awad. 2018. Osiris: A low-cost mechanism to enable restoration of secure non-volatile memories. In Proceedings of the 51st International Symposium on Microarchitecture (MICRO’18).
[48]
Doe Hyun Yoon and Mattan Erez. 2009. Memory mapped ECC: Low-cost error protection for last level caches. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09).
[49]
Vinson Young, Prashant Nair, and Moinuddin Qureshi. 2015. DEUCE: Write-efficient encryption for non-volatile memories. ACM SIGARCH Comput. Arch. News 43, 1 (Mar.2015), 33–44.
[50]
Jianhui Yue and Yifeng Zhu. 2013. Accelerating write by exploiting PCM asymmetries. In Proceedings of the IEEE 19th International Symposium on High Performance Computer Architecture (HPCA’13).
[51]
Ping Zhou, Bo Zhao, Jun Yang, and Youtao Zhang. 2009. A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th Annual International Symposium on Computer Architecture (ISCA’09).
[52]
Yanqi Zhou, Ramnatthan Alagappan, Amirsaman Memaripour, Anirudh Badam, and David Wentzlaff. 2017. HNVM: Hybrid NVM Enabled Datacenter Design and Optimization. Microsoft Research TR8 (Feb.2017).
[53]
Abu Zubair and Amro Awad. 2019. Anubis: Ultra-low overhead and recovery time for secure non-volatile memories. In Proceedings of the 46th International Symposium on Computer Architecture (ISCA’19).
[54]
Abu Zubair, Sudhanva Gurumurthi, Vilas Sridharan, and Amro Awad. 2021. Soteria: Towards resilient integrity-protected and encrypted non-volatile memories. In Proceedings of the 54th International Symposium on Microarchitecture (MICRO’21).
[55]
Pengfei Zuo, Yu Hua, and Yuan Xie. 2019. SuperMem: Enabling application-transparent secure persistent memory with low overheads. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’19).
[56]
Pengfei Zuo, Yu Hua, Ming Zhao, Wen Zhou, and Yuncheng Guo. 2018. Improving the performance and endurance of encrypted non-volatile main memory through deduplicating writes. In Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’18).
Index Terms
- FSDedup: Feature-Aware and Selective Deduplication for Improving Performance of Encrypted Non-Volatile Main Memory
Recommendations
Redesign the Memory Allocator for Non-Volatile Main Memory
Special Issue on Hardware and Algorithms for Learning On-a-chip and Special Issue on Alternative Computing SystemsThe non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. ...
A high performance file system for non-volatile main memory
EuroSys '16: Proceedings of the Eleventh European Conference on Computer SystemsEmerging non-volatile main memories (NVMMs) provide data persistence at the main memory level. To avoid the double-copy overheads among the user buffer, the OS page cache, and the storage layer, state-of-the-art NVMM-aware file systems bypass the OS ...
Improving the performance and endurance of encrypted non-volatile main memory through deduplicating writes
MICRO-51: Proceedings of the 51st Annual IEEE/ACM International Symposium on MicroarchitectureNon-volatile memory (NVM) technologies are considered as promising candidates of the next-generation main memory. However, the non-volatility of NVMs leads to new security vulnerabilities. For example, it is not difficult to access sensitive data stored ...
Comments
Information & Contributors
Information
Published In
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].
Publisher
Association for Computing Machinery
New York, NY, United States
Publication History
Published: 06 August 2024
Online AM: 01 May 2024
Accepted: 15 April 2024
Revised: 22 March 2024
Received: 22 October 2023
Published in TOS Volume 20, Issue 4
Check for updates
Author Tags
Qualifiers
- Research-article
Funding Sources
- National Key R&D Program of China
- National Natural Science Foundation of China
- Open Project Program of Wuhan National Laboratory for Optoelectronics
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- View Citations1Total Citations
- 317Total Downloads
- Downloads (Last 12 months)317
- Downloads (Last 6 weeks)43
Reflects downloads up to 23 Dec 2024
Other Metrics
Citations
Cited By
View all- Hamandawana PCho DChung T(2024)Speed-Dedup: A New Deduplication Framework for Enhanced Performance and Reduced Overhead in Scale-Out StorageElectronics10.3390/electronics1322439313:22(4393)Online publication date: 9-Nov-2024
View Options
Login options
Check if you have access through your login credentials or your institution to get full access on this article.
Sign in