Bottleneck equipment management: simulating test program methods in semiconductor assembly test factories

Significant opportunities for improvement in semiconductor Assembly/Test (A/T) manufacturing reside in the Test areas. These Test areas can very often be the system constraint, due to complex testing policies, bin-to-order mapping, and cost. A very difficult problem for both researchers and manufacturers is to determine the best methods for assigning test programs for lots on these test equipment. To answer these problems, Intel has produced dynamic discrete event simulation models that consider multiple wafer types, multiple end products, multiple test program methods, and binning policies of end products according to the tested performance of the die. This model does not require modeling specific manufacturing equipment and operator activities, only detailed logic of test program and binning policies. The quantitative output data from this model provides the relative decision support necessary to determine what methods work best for Intel, given other costs and business drivers.