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- invited-talkMarch 2024
Solving the Physical Challenges for the Next Generation of Safety Critical & High Reliability Systems
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPage 267https://doi.org/10.1145/3626184.3635287Silicon systems have been part of automobiles for a long time. The physical design methodology to address the quality, reliability, and safety challenges of these systems are common knowledge in the leading automotive semiconductor companies. The rise of ...
- invited-talkMarch 2024
Unified 3D-IC Multi-Chiplet System Design Solution
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPage 83https://doi.org/10.1145/3626184.3635279With the advancements in 2.5/3D fabrication offered by Foundry Technologies for unleashing computing power, EDA tools must adapt and take a direction to be more integrated and IC centric for multi-chiplet system design. 3D stacking introduces extra ...
- invited-talkMarch 2024
AI for EDA/Physical Design: Driving the AI Revolution: The Crucial Role of 3D-IC
ISPD '24: Proceedings of the 2024 International Symposium on Physical DesignPage 113https://doi.org/10.1145/3626184.36352753D Integrated Circuits (3D-ICs) represent a significant advancement in semiconductor technology, offering enhanced functionality in smaller form factors, improved performance, and cost reductions. These 3D-ICs, particularly those utilizing Through-...
- invited-talkApril 2022
Challenges for Automating Package Routing
ISPD '22: Proceedings of the 2022 International Symposium on Physical DesignPages 193–194https://doi.org/10.1145/3505170.3511474Package routing is typically done by semi-auto or manual manners in order to meet several customized requests for different design styles. However, in recent years, the scale of package designs rapidly enlarges, and routing rules become more and more ...
- posterAugust 2014
Unlocking the true potential of 3D CPUs with micro-fluidic cooling
ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and designPages 323–326https://doi.org/10.1145/2627369.2627666As technology scaling is coming to an end, 3D integration is a promising technology to continue transistor density scaling in the future and facilitate new architectural designs. However heat removal is a serious chalenge in 3D ICs. A promising solution ...
- research-articleMarch 2014
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts
ISPD '14: Proceedings of the 2014 on International symposium on physical designPages 55–62https://doi.org/10.1145/2560519.2560532In 3D ICs, TSV cross coupling can seriously degrade circuit performance if it is not sufficiently considered in a design. Cross coupling is heavily dependent on how TSVs are placed, and should be considered during the floorplanning of the chip. In this ...
- posterMay 2013
Co-optimization of TSV assignment and micro-channel placement for 3D-ICs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 337–338https://doi.org/10.1145/2483028.2483131The three dimensional circuit (3D-IC) brings forth new challenges to physical design such as allocation and management of through-silicon-vias (TSVs). Meanwhile, the thermal issues in 3D-IC becomes significant necessitating the use of active cooling ...
- research-articleMay 2013
Thermal stress aware 3D-IC statistical static timing analysis
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 281–286https://doi.org/10.1145/2483028.2483110It is widely known that fabrication and thermal variations influence circuit delay. In three dimensional circuits (3D-ICs), due to the incorporation of through-silicon-vias (TSVs), thermal stress also becomes an increasing contributor to gate delay. As ...
- research-articleMay 2013
Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIPages 275–280https://doi.org/10.1145/2483028.2483109In 3D ICs, interlayer communication is achieved using through-silicon-vias (TSVs), which can suffer from cross coupling if placed naïvely. In this paper, cross coupling between TSVs is modeled, and a chip-scale TSV coupling mitigation scheme is ...
- research-articleMarch 2012
TSV-constrained micro-channel infrastructure design for cooling stacked 3D-ICs
ISPD '12: Proceedings of the 2012 ACM international symposium on International Symposium on Physical DesignPages 113–118https://doi.org/10.1145/2160916.2160941Micro-channel based liquid cooling has significant capability of removing high density heat in 3D-ICs. The conventional micro-channel structures investigated for cooling 3D-ICs use straight channels. However, the presence of TSVs which form obstacles to ...