research-article

Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs

Authors:

Caleb Serafy,

Bing Shi,

Ankur SrivastavaAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 275 - 280

https://doi.org/10.1145/2483028.2483109

Published: 02 May 2013 Publication History

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Abstract

In 3D ICs, interlayer communication is achieved using through-silicon-vias (TSVs), which can suffer from cross coupling if placed naïvely. In this paper, cross coupling between TSVs is modeled, and a chip-scale TSV coupling mitigation scheme is presented using TSV shielding. A geometric coupling model is developed which is simple enough to quickly estimate the pairwise coupling between TSVs, unlike circuit models of coupling that have been proposed in previous works. Our geometric model's ability to make fast accurate estimations of chip-scale cross coupling make it a good model to use for shield placement optimization.

A shield placement algorithm is presented which reduces TSV coupling by formulating a min cost flow (MCF) problem based on the proposed model. Our algorithm is compared to another shield placement algorithm presented in [9] which is based on a circuit model of coupling. Experimental results show that the algorithm proposed here is able to reduce the total cross coupling in a layout an average of 4.59x more than the other algorithm while using the same number of shields. Alternatively, our algorithm uses an average of 88% less shields to shield a layout to the same degree as the shielding schemes produced by the other algorithm.

References

[1]

Ansys HFSS. http://www.ansys.com/Products/Simulation+Technology/Electromagnetics.

Google Scholar

[2]

IBM-Place 2.0 Benchmarks. http://er.cs.ucla.edu/benchmarks/ibm-place2/.

Google Scholar

[3]

MCF - A network simplex implementation. http://typo.zib.de/opt-long_projects/Software/Mcf/.

Google Scholar

[4]

J. Cho, J. Kim, T. Song, et al. Through silicon via (TSV) shielding structures. In Electrical Performance of Electronic Packaging and Systems (EPEPS), 2010 IEEE 19th Conf. on.

Google Scholar

[5]

J. Cho, E. Song, K. Yoon, et al. Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring. Components, Packaging and Manufacturing Technology, IEEE Trans. on.

Google Scholar

[6]

N. Khan, S. Alam, and S. Hassoun. Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs. In Quality Electronic Design (ISQED), 2011 12th Int. Symposium on.

Google Scholar

[7]

N. Khan, S. Alam, and S. Hassoun. Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. In 3D System Integration, 2009. 3DIC 2009. IEEE Int. Conf. on.

Google Scholar

[8]

Y.-J. Lee and S. K. Lim. Timing analysis and optimization for 3D stacked multi-core microprocessors. In 3D Systems Integration Conf. (3DIC), 2010 IEEE Int.

Google Scholar

[9]

C. Liu, T. Song, J. Cho, et al. Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC. In Proc. of the 2011 48th Design Automation Conf. ACM.

Digital Library

Google Scholar

[10]

C. Liu, T. Song, and S. K. Lim. Signal integrity analysis and optimization for 3D ICs. In Quality Electronic Design (ISQED), 2011 12th Int. Symposium on.

Google Scholar

[11]

G. Loh. 3D-Stacked Memory Architectures for Multi-core Processors. In Computer Architecture, 2008. ISCA '08. 35th Int. Symposium on.

Digital Library

Google Scholar

Cited By

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Xie YBao CSerafy CLu TSrivastava ATehranipoor M(2016)Security and Vulnerability Implications of 3D ICsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2016.25504602:2(108-122)Online publication date: 1-Apr-2016
https://doi.org/10.1109/TMSCS.2016.2550460
Serafy CSrivastava A(2015)TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238575434:4(554-562)Online publication date: Apr-2015
https://doi.org/10.1109/TCAD.2014.2385754
Serafy CSrivastava ASze CDavoodi A(2014)Coupling-aware force driven placement of TSVs and shields in 3D-IC layoutsProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560532(55-62)Online publication date: 30-Mar-2014
https://dl.acm.org/doi/10.1145/2560519.2560532
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Index Terms

Geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Through silicon via (TSV) cross coupling can seriously degrade circuit performance of 3-D ICs if it is not considered during design. In this paper, we propose two algorithms which combine coupling-aware TSV placement with shield insertion to yield better ...

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Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 May 2013

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GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 271 of 1,008 submissions, 27%

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Xie YBao CSerafy CLu TSrivastava ATehranipoor M(2016)Security and Vulnerability Implications of 3D ICsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2016.25504602:2(108-122)Online publication date: 1-Apr-2016
https://doi.org/10.1109/TMSCS.2016.2550460
Serafy CSrivastava A(2015)TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global PlacementIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.238575434:4(554-562)Online publication date: Apr-2015
https://doi.org/10.1109/TCAD.2014.2385754
Serafy CSrivastava ASze CDavoodi A(2014)Coupling-aware force driven placement of TSVs and shields in 3D-IC layoutsProceedings of the 2014 on International symposium on physical design10.1145/2560519.2560532(55-62)Online publication date: 30-Mar-2014
https://dl.acm.org/doi/10.1145/2560519.2560532
Serafy CShi BSrivastava A(2014)A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICsIntegration10.1016/j.vlsi.2013.11.00447:3(307-317)Online publication date: Jun-2014
https://doi.org/10.1016/j.vlsi.2013.11.004

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Recommendations

TSV-aware analytical placement for 3D IC designs

Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs

TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global Placement

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