In concurrent online BIST, testing is conducted simultaneously during normal functional operation. A fault model enables a structural test to be undertaken for a long time while simultaneously identifying critical faults. As a result of continuous ...

This study applies artificial neural networks (ANNs) to increase stuck-at and delay fault coverage of logic built-in self-test (LBIST) through test point insertion (TPI). Increasing TPI quality is essential for modern logic circuits, but the ...

This work introduced a new BIST scheme under a functional test approach. It solves the problem of determining in-field the specifications of lowpass filters embedded in PSoC1 devices with zero hardware overhead. The user can implement the BIST we ...

Offline and online built-in self-test (BIST) designs are low-cost platforms to test very complex modern chips. The offline BIST design embeds the test pattern generator (TPG) into the chip to be activated in the test time. On the other hand, the ...

In this study, we design two-way binary-Gray codes encoding/decoding circuit. Two-way means that the circuit can be function programmed as either binary-to-Gray or Gray-to-binary code transformations. A self-checking capability is also embedded in ...

We implemented pseudo-linear feedback shift-register-based physical unclonable functions (PL-PUFs) on silicon and analyzed their performances in terms of reproducibility, uniqueness, and resistance to machine-learning attacks. A PL-PUF ...

• PL-PUF is implemented on silicon and achieves sufficiently high performance.
• ...

Massive test data volume and excessive test power consumption have become two strict challenges for very large scale integrated circuit testing. In BIST architecture, the unspecified bits are randomly filled by LFSR reseeding-based test compression ...

The paper presents the use of Genetic Algorithm to search for non-linear Autonomous Test Structures (ATS) in Built-In Testing approach. Such structures can include essentially STP and CSTP and their modifications. Non-linear structures are more ...

This paper describes a design for testability technique for second-order bandpass operational transconductance amplifier and capacitor (OTA-C) filters using an oscillation-based test topology. The oscillation-based test structure is a vectorless output ...

Integrated circuits testing of IP cores embedded in contemporary SoCs is costly. One common strategy to lower the cost of test is to reduce test time through concurrent testing. At present, it is well known that this approach necessitates the cores ...

Mobile Wide-I/O DRAMs are used in smartphones, tablets, handheld gaming consoles and other mobile devices. The main benefit of the Wide-I/O DRAM over its predecessors (such as LPDDRx DRAMs) is that it offers more bandwidth at lower power. In this paper, ...

This paper presents an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The ...

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based Logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working ...

The application of single input change (SIC) pairs of test patterns is very efficient for sequential, i.e. stuck-open and delay fault testing. In this paper a novel implementation for the application of SIC pairs is presented and a formal proof of its ...

This paper presents and evaluates a new built-in current sensor used to detect n-well single-event transients (SETs) induced by radiation strikes in integrated circuits (IC). A 28 nm bulk CMOS test chip containing the proposed sensor design was ...

A low power test-per-clock built-in self-test (BIST) scheme based on 2-bit TRC is presented in this paper. The low power during testing can be obtained by selectively activating multi 2-bit twisting ring counters (AM2B-TRC). The optimal number of ...

Input vector monitoring concurrent on-line BIST based on multilevel decoding logic is an attractive approach to reduce hardware overhead. In this paper, a novel optimization scheme is proposed for further reducing the hardware overhead of the decoding ...

Power consumption has become a very important consideration during integrated circuit (IC) design and test. During test, it can far exceed the values reached during normal operation and, thus, lead to temperatures above the allowed threshold. Without ...

In this paper we present a Built-In Self-Test (BIST) technique to measure the natural resonance frequency of oscillators which are design to set a much higher than the working speed of most of the current Automated Test Equipment (ATE). Based on an ...

Graphics Processing Unit (GPU) requires I/O bandwidth of the order of Gbps which can be met by implementation of High Speed Serializer/Deserializer differential I/Os with clock embedded in data stream, traditionally tested using functional Built In Self ...