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- research-articleJuly 2017
On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE
ACM Transactions on Architecture and Code Optimization (TACO), Volume 14, Issue 2Article No.: 18, Pages 1–24https://doi.org/10.1145/3090634Increasing instruction-level parallelism is regaining attractiveness within the microprocessor industry.
The {Early | Out-of-order | Late} Execution (EOLE) microarchitecture and Differential Value TAgged GEometric (D-VTAGE) value predictor were recently ...
- research-articleOctober 2013
A unified view of non-monotonic core selection and application steering in heterogeneous chip multiprocessors
PACT '13: Proceedings of the 22nd international conference on Parallel architectures and compilation techniquesPages 133–144A single-ISA heterogeneous chip multiprocessor (HCMP) is an attractive substrate to improve single-thread performance and energy efficiency in the dark silicon era. We consider HCMPs comprised of non-monotonic core types where each core type is ...
- articleJuly 2012
Underclocked Software Prefetching: More Cores, Less Energy
Power consumption is a concern for helper-thread prefetching that uses extra cores to speed up the single-thread execution, because power consumption increases with each additional core. This article analyzes the impact of using power-saving techniques ...
- ArticleJune 2012
VSCP: A Cache Controlling Method for Improving Single Thread Performance in Multicore System
HPCC '12: Proceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and SystemsPages 161–168https://doi.org/10.1109/HPCC.2012.30Single thread performance is still a matter of concern even for multicore systems. Making good advantage of on-chip cache memory is critical in improving single thread performance. However, as the distributed layout of on-chip cache, single-threaded ...
- research-articleJune 2012
Near-threshold operation for power-efficient computing?: it depends...
DAC '12: Proceedings of the 49th Annual Design Automation ConferencePages 1159–1163https://doi.org/10.1145/2228360.2228573While it has long been argued that near-threshold (~0.5V) operation of CMOS technologies can dramatically improve power efficiency, widespread application of such low voltage operation to VLSI systems has yet to materialize. This is due in part to ...
- posterMay 2012
CoreSymphony architecture
CF '12: Proceedings of the 9th conference on Computing FrontiersPages 249–252https://doi.org/10.1145/2212908.2212945We propose CoreSymphony architecture, which aims at balancing single-thread performance and multi-thread performance on CMPs. The former version of CoreSymphony had complex branch predictor, re-order buffer, and in-order state management mechanism. In ...
- research-articleMarch 2011
Inter-core prefetching for multicore processors using migrating helper threads
ASPLOS XVI: Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systemsPages 393–404https://doi.org/10.1145/1950365.1950411Multicore processors have become ubiquitous in today's systems, but exploiting the parallelism they offer remains difficult, especially for legacy application and applications with large serial components. The challenge, then, is to develop techniques ...
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ACM SIGARCH Computer Architecture News: Volume 39 Issue 1ACM SIGPLAN Notices: Volume 46 Issue 3 - research-articleJune 2010
Software data spreading: leveraging distributed caches to improve single thread performance
PLDI '10: Proceedings of the 31st ACM SIGPLAN Conference on Programming Language Design and ImplementationPages 460–470https://doi.org/10.1145/1806596.1806648Single thread performance remains an important consideration even for multicore, multiprocessor systems. As a result, techniques for improving single thread performance using multiple cores have received considerable attention. This work describes a ...
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ACM SIGPLAN Notices: Volume 45 Issue 6 - ArticleSeptember 2009
Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading
- Carlos Madriles,
- Pedro Lopez,
- Josep Maria Codina,
- Enric Gibert,
- Fernando Latorre,
- Alejandro Martinez,
- Raul Martinez,
- Antonio Gonzalez
PACT '09: Proceedings of the 2009 18th International Conference on Parallel Architectures and Compilation TechniquesPages 15–25https://doi.org/10.1109/PACT.2009.27Industry is moving towards multi-core designs as we have hit the memory and power walls. Multi-core designs are very effective to exploit thread-level parallelism (TLP) but do not provide benefits when executing serial code (applications with low TLP, ...
- research-articleJune 2009
Boosting single-thread performance in multi-core systems through fine-grain multi-threading
- Carlos Madriles,
- Pedro López,
- Josep M. Codina,
- Enric Gibert,
- Fernando Latorre,
- Alejandro Martinez,
- Raúl Martinez,
- Antonio Gonzalez
ISCA '09: Proceedings of the 36th annual international symposium on Computer architecturePages 474–483https://doi.org/10.1145/1555754.1555813Industry has shifted towards multi-core designs as we have hit the memory and power walls. However, single thread performance remains of paramount importance since some applications have limited thread-level parallelism (TLP), and even a small part with ...
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ACM SIGARCH Computer Architecture News: Volume 37 Issue 3 - research-articleJune 2009
Dynamic parallelization of single-threaded binary programs using speculative slicing
ICS '09: Proceedings of the 23rd international conference on SupercomputingPages 158–168https://doi.org/10.1145/1542275.1542302The performance of single-threaded programs and legacy binary code is of critical importance in many everyday applications. However, neither can hardware multi-core processors directly speed up single-threaded programs, nor can software automatic ...
