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On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE

Authors:

Fernando A. Endo,

André SeznecAuthors Info & Claims

ACM Transactions on Architecture and Code Optimization (TACO), Volume 14, Issue 2

Article No.: 18, Pages 1 - 24

https://doi.org/10.1145/3090634

Published: 12 July 2017 Publication History

Abstract

Increasing instruction-level parallelism is regaining attractiveness within the microprocessor industry.

The {Early | Out-of-order | Late} Execution (EOLE) microarchitecture and Differential Value TAgged GEometric (D-VTAGE) value predictor were recently introduced to solve practical issues of Value Prediction (VP). In particular, they remove the most significant difficulties that forbade an effective VP hardware.

In this study, we present a detailed evaluation of the potential of VP in the context of EOLE/D-VTAGE and different compiler options. Our study shows that if no single general rule always applies—more optimization might sometimes lead to more performance—unoptimized codes often get a large benefit from the prediction of redundant loads.

References

[1]

ARM. 2015. ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (a.h ed.). ARM. ARM DDI 0487A.h (ID092915).

[2]

Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The gem5 simulator. SIGARCH Computer Architecture News 39, 2 (May 2011), 1--7.

Digital Library

[3]

Martin Burtscher and Benjamin G. Zorn. 1999. Exploring last n value prediction. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT’99). 66--76.

[4]

Brad Calder, Glenn Reinman, and Dean M. Tullsen. 1999. Selective value prediction. In Proceedings of the 26th International Symposium on Computer Architecture (ISCA’99). 64--74.

[5]

George Z. Chrysos and Joel S. Emer. 1998. Memory dependence prediction using store sets. In Proceedings of the 25th Annual International Symposium on Computer Architecture (ISCA’98). IEEE Computer Society, Washington, DC, 142--153.

[6]

Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. 2011. Dark silicon and the end of multicore scaling. In Proceedings of the 38th Annual International Symposium on Computer Architecture (ISCA’11). ACM, New York, 365--376.

Digital Library

[7]

Freddy Gabbay. 1996. Speculative Execution Based on Value Prediction. Ph.D. dissertation. Technion-IIT, Department of Electrical Engineering.

[8]

Freddy Gabbay and Avi Mendelson. 1998. Using value prediction to increase the power of speculative execution hardware. ACM Transactions on Computer Systems 16, 3 (Aug. 1998), 234--270.

Digital Library

[9]

José González and Antonio González. 1996. Memory Address Prediction for Data Speculation. Technical Report. Universitat Politecnica de Catalunya. UPC-DAC-1996-50.

[10]

Intel. 2015. Intel 64 and IA-32 Architectures Optimization Reference Manual.

[11]

Ilhyun Kim and Mikko H. Lipasti. 2004. Understanding scheduling replay schemes. In IEE Proceedings-Software (HPCA’04). 198--209.

Digital Library

[12]

Mikko H. Lipasti and John Paul Shen. 1996. Exceeding the dataflow limit via value prediction. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO’96). IEEE Computer Society, Washington, DC, 226--237.

[13]

Mikko H. Lipasti, Christopher B. Wilkerson, and John Paul Shen. 1996. Value locality and load value prediction. SIGPLAN Notices 31, 9 (Sept. 1996), 138--147.

Digital Library

[14]

Rick Merritt. 2009. ARM CTO: Power surge could create ‘dark silicon’. Retrieved from http://www.eetimes.com/news/design/showArticle.jhtml?articleID=220900080.

[15]

Pierre Michaud. 2016. Best-offset hardware prefetching. In Proceedings of the International Symposium on High-Performance Computer Architecture(HPCA’16).

[16]

Tarun Nakra, Rajiv Gupta, and Mary Lou Soffa. 1999. Global context-based value prediction. In Proceedings of the 5th International Symposium on High-Performance Computer Architecture (HPCA’99). 4--12.

[17]

Tony Nowatzki, Jaikrishnan Menon, Chen-Han Ho, and Karthikeyan Sankaralingam. 2015. Architectural simulators considered harmful. IEEE Micro 35, 6 (Nov. 2015), 4--12.

Digital Library

[18]

Arthur Perais and André Seznec. 2014a. EOLE: Paving the way for an effective implementation of value prediction. In Proceedings of the 41st Annual International Symposium on Computer Architecuture (ISCA’14). IEEE Press, Piscataway, NJ, 481--492.

Digital Library

[19]

Arthur Perais and André Seznec. 2014b. Practical data value speculation for future high-end processors. In Proceedings of the IEEE 20th International Symposium on High Performance Computer Architecture (HPCA’14). 428--439.

[20]

Arthur Perais and André Seznec. 2015a. BeBoP: A cost effective predictor infrastructure for superscalar value prediction. In Proceedings of the IEEE 21st International Symposium on High Performance Computer Architecture (HPCA’15). 13--25.

[21]

Arthur Perais and André Seznec. 2015b. EOLE: Toward a practical implementation of value prediction. IEEE Micro 35, 3 (May 2015), 114--124.

[22]

Arthur Perais and André Seznec. 2016. EOLE: Combining static and dynamic scheduling through value prediction to reduce complexity and increase performance. TACM Transactions on Computer Systems (Feb. 2016), 34.

Digital Library

[23]

Erez Perelman, Greg Hamerly, Michael Van Biesbrouck, Timothy Sherwood, and Brad Calder. 2003. Using simpoint for accurate and efficient simulation. SIGMETRICS Performance Evaluation Review 31, 1 (June 2003), 318--319.

Digital Library

[24]

Nicholas Riley and Craig Zilles. 2006. Probabilistic counter updates for predictor hysteresis and stratification. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA’06). 110--120.

[25]

Y. Sazeides and J. E. Smith. 1997. The predictability of data values. In Proceedings of the 30th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’97). 248--258.

[26]

Yiannakis Sazeides, Stamatis Vassiliadis, and James E. Smith. 1996. The performance potential of data dependence speculation 8 collapsing. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO 29). IEEE Computer Society, Washington, DC, 238--247. http://dl.acm.org/citation.cfm?id=243846.243890.

[27]

André Seznec and Pierre Michaud. 2006. A case for (partially) tagged geometric history length branch prediction. Journal of Instruction Level Parallelism 8 (2006), 1--23.

Cited By

Yang LHuang LZheng ZThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)Confidence Counter Modelling for Value PredictorProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590319(221-222)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590319
Oliveira GGomez-Luna JOrosa LGhose SVijaykumar NFernandez ISadrosadati MMutlu O(2021)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement BottlenecksIEEE Access10.1109/ACCESS.2021.31109939(134457-134502)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3110993
Orosa LAzevedo RMutlu O(2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
https://dl.acm.org/doi/10.1145/3239567
Show More Cited By

Index Terms

On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE
1. Computer systems organization
  1. Architectures
    1. Serial architectures
      1. Pipeline computing
2. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
      1. Emerging architectures

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cover image ACM Transactions on Architecture and Code Optimization

ACM Transactions on Architecture and Code Optimization Volume 14, Issue 2

June 2017

259 pages

ISSN:1544-3566

EISSN:1544-3973

DOI:10.1145/3086564

Editor:
Koen De Bosschere
Ghent University

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Copyright © 2017 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 12 July 2017

Accepted: 01 May 2017

Revised: 01 March 2017

Received: 01 October 2016

Published in TACO Volume 14, Issue 2

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Cited By

Yang LHuang LZheng ZThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)Confidence Counter Modelling for Value PredictorProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590319(221-222)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590319
Oliveira GGomez-Luna JOrosa LGhose SVijaykumar NFernandez ISadrosadati MMutlu O(2021)DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement BottlenecksIEEE Access10.1109/ACCESS.2021.31109939(134457-134502)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3110993
Orosa LAzevedo RMutlu O(2018)AVPPACM Transactions on Architecture and Code Optimization10.1145/323956715:4(1-30)Online publication date: 7-Dec-2018
https://dl.acm.org/doi/10.1145/3239567
Mittal S(2017)A survey of value prediction techniques for leveraging value localityConcurrency and Computation: Practice and Experience10.1002/cpe.425029:21Online publication date: 11-Sep-2017
https://doi.org/10.1002/cpe.4250

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