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Using value prediction to increase the power of speculative execution hardware

Authors:

Freddy Gabbay and

Avi MendelsonAuthors Info & Claims

ACM Transactions on Computer Systems (TOCS), Volume 16, Issue 3

Pages 234 - 270

https://doi.org/10.1145/290409.290411

Published: 01 August 1998 Publication History

Abstract

This article presents an experimental and analytical study of value prediction and its impact on speculative execution in superscalar microprocessors. Value prediction is a new paradigm that suggests predicting outcome values of operations (at run-time ) and using these predicted values to trigger the execution of true-data-dependent operations speculatively. As a result, stals to memory locations can be reduced and the amount of instruction-level parallelism can be extended beyond the limits of the program's dataflow graph. This article examines the characteristics of the value prediction concept from two perspectives: (1) the related phenomena that are reflected in the nature of computer programs and (2) the significance of these phenomena to boosting instruction-level parallelism of superscalar microprocessors that support speculative execution. In order to better understand these characteristics, our work combines both analytical and experimental studies.

References

[1]

ADAM, T. L., CHANDY, K. M., AND DICKSON, J. R. 1974. A comparison of list scheduling for parallel processing systems. Commun. ACM 17, 12 (Dec.), 685-690.

[2]

AHO, A. V., SETHI, R., AND ULLMAN, J. D. 1986. Compilers: Principles, Techniques, and Tools. Addison-Wesley Longman Publ. Co., Inc., Reading, MA.

[3]

AIKEN, A. AND NICOLAU, A. 1988. Perfect pipelining: A new loop parallelization technique. In Proceedings of the 2nd European Symposium on Programming (New York, Mar.), H. Ganzinger, Ed. 221-235.

[4]

BLAINEY, R. J. 1994. Instruction scheduling in the TOBEY compiler. IBM J. Res. Dev. 38, 5 (Sept.), 577-593.

[5]

CHANG, P.-Y., EVERS, M., AND PATT, Y. N. 1996. Improving branch prediction accuracy by reducing pattern history table interference. In Proceedings of the Conference on Parallel Architectures and Compilation Techniques (PACT). 48-57.

[6]

CHARLESWORTH, A. E. 1981. An approach to scientific array processing: The architectural design of the AP-120B/FPS family. Computer 14, 9 (Sept.), 18-27.

[7]

CHEN, T. F. AND BEAR, J. L. 1995. Effective hardware-based data prefetching for highperformance processors. IEEE Trans. Comput. 44, 5 (May), 609-623.

[8]

DAVIDSON, S., LANDSKOV, D., SHRIVER, B. D., AND MALLET, P.W. 1981. Some experiments in local microcode compaction for horizontal machines. IEEE Trans. Comput. C-30, 7 (July), 460-477.

[9]

DIEP, T. A., NELSON, C., AND SHEN, J. P. 1995. Performance evaluation of the PowerPC 620 micro-architecture. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95, Santa Margherita Ligure, Italy, June 22-24). ACM Press, New York, NY, 163-174.

[10]

DITZEL, D. R. AND MCLELLAN, H. R. 1987. Branch folding in the CRISP microprocessor: Reducing branch delay to zero. In Proceedings of the 14th Annual International Symposium on Computer Architecture (ISCA '87, Pittsburgh, PA, June 2-5), D. St. Clair, Ed. ACM Press, New York, NY, 2-8.

[11]

EDMONDSON, J. H., RUBINFELD, P., PRESTON, R., AND RAJAGOPALAN, V. 1995. Superscalar instruction execution in the 21164 Alpha microprocessor. IEEE Micro 15, 2 (Apr.), 33-43.

[12]

ELLIS, J. R. 1986. Bulldog: A Compiler for VLSIArchitectures. MIT Press, Cambridge, MA.

[13]

FISHER, J.A. 1979. The optimum of horizontal microcode within and beyond basic blocks: An application of processor scheduling with resources. Ph.D. dissertation, Tech. Rep. COO-3077-161. Courant Mathematics and Computing Laboratory, New York University, New York, NY.

[14]

FISHER, J. A. AND FREUDENBERGER, S. M. 1992. Predicting conditional branch directions from previous runs of a program. In Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-V, Boston, MA, Oct. 12-15). ACM Press, New York, NY, 85-95.

[15]

FUAND, J. W. C. AND PATEL, J. g. 1992. Stride directed prefetching in scalar processors. In Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO 25, Portland, OR, Dec. 1-4). IEEE Computer Society Press, Los Alamitos, CA, 102-110.

[16]

GABBAY, F. AND MENDELSON, A. 1996. Speculative execution based on value prediction. Tech. Rep. 1080. Electrical Engineering Department, Technion--Israel Institute of Technology, Haifa, Israel.

[17]

GABBAY, F. AND MENDELSON, A. 1997. Can program profiling support value prediction?. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture. ACM, New York, NY.

[18]

GABBAY, F. AND MENDELSON, A. 1998. The effect of instruction-fetch bandwidth on value prediction. In Proceedings of the 25th International Symposium on Computer Architecture.

[19]

GONZALES, J. AND GONZALES, A. 1997. Speculative execution via address prediction and data prefetching. In Proceedings of the 11th International Conference on Supercomputing. 196-203.

[20]

GWENNAP, L. 1995. Intel's P6 uses decoupled superscalar design. Microprocess. Rep. 9, 2 (Feb.).

[21]

KELLER, R. M. 1975. Look-ahead processors. ACM Comput. Surv. 7, 4 (Dec.), 177-195.

[22]

JOHNSON, M. 1990. Superscalar Microprocessor Design. Prentice Hall, Englewood Cliffs, NJ.

[23]

LAM, M. S. 1988. Software pipelining: An effective scheduling technique for VLIW machines. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI '88, Atlanta, GA, June 22-24), R. L. Wexelblat, Ed. ACM Press, New York, NY, 318-328.

[24]

LAM, M. S. 1989. A Systolic Array Optimizing Compiler. Kluwer Academic Publishers, Hingham, MA.

[25]

LIPASTI, M. g., WILKERSON, C. B., AND SHEN, J. P. 1996a. Value locality and load value prediction. In Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VII). ACM Press, New York, NY.

[26]

LIPASTI, M. g., WILKERSON, C. B., AND SHEN, J. P. 1996b. Exceeding the dataflow limit via value prediction. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture. ACM, New York, NY.

[27]

MCFARLING, S. AND HENNESSY, J. 1986. Reducing the cost of branches. In Proceedings of the 13th Annual International Symposium on Computer Architecture (ISCA '86, Tokyo, Japan, June 2-5). IEEE Computer Society Press, Los Alamitos, CA, 396-403.

[28]

PINTER, S. S. AND YOAZ, A. 1996. Tango: A hardware-based data prefetching technique for super-scalar processors. In Proceedings of the 29th Annual ACM/IEEE International Symposium on Microarchitecture. ACM, New York, NY.

[29]

RAU, B. R. AND GLAESER, C. D. 1981. Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing. In Proceedings of the 14th Annual Workshop on Microprogramming. 183-198.

[30]

SIMONE, M., ESSEN, A., IKE, A., KRISHNAMOORTHY, A., MARUYAMA, T., PATKAR, N., RAMASWAMI, M., SHEBANOW, M., THIRUMALAISWAMY, V., AND TOVEY, D. 1995. Implementation trade-offs in using restricted data flow architecture in high performance RISC microprocessors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture (ISCA '95, Santa Margherita Ligure, Italy, June 22-24). ACM Press, New York, NY, 151-162.

[31]

SUN MICROSYSTEMS. 1992. Introduction to Shade. Tech. Rep. 415-960-1300 (Revision A of 1/Apr/92). Sun Microsystems, Inc., Mountain View, CA.

[32]

SMITH, A. AND LEE, J. 1984. Branch prediction strategies and branch-target buffer design. Computer 17, 1 (Jan.), 6-22.

[33]

SMITH, J. E. 1981. A study of branch prediction techniques. In Proceedings of the 8th International Symposium on Computer Architecture.

[34]

TOMASULO, R. M. 1967. An efficient algorithm for exploiting multiple arithmetic units. IBM J. Res. Dev. 11, 1 (Jan.), 25-33.

[35]

WALL, D.W. 1991. Limits of instruction-level parallelism. In Proceedings of the 4th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV, Santa Clara, CA, Apr. 8-11). ACM Press, New York, NY, 248-259.

[36]

WEISS, S. AND SMITH, J. E. 1987. A study of scalar compilation techniques for pipelined supercomputers. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems (APLOS II, Palo Alto, CA, Oct. 5-8), R. Katz, Ed. IEEE Computer Society Press, Los Alamitos, CA, 105-109.

[37]

YEH, T.-Y. AND PATT, Y. N. 1991. Two-level adaptive training branch prediction. In Proceedings of the 24th Annual International Symposium on Microarchitecture (MICRO 24, Albuquerque, NM, Nov. 18-20). ACM Press, New York, NY, 51-61.

[38]

YEH, T. Y. AND PATT, Y. N. 1992. Alternative implementation of two-level adaptive branch prediction. In Proceedings of the 19th Annual International Symposium on Computer Architecture (ISCA '92, Gold Coast, Australia, May 19-21). ACM Press, New York, NY, 124-134.

[39]

YEH, T. Y. AND PATT, Y. N. 1993. A comparison of dynamic branch predictors that uses two levels of branch history. In Proceedings of the 20th Annual International Symposium on Computer Architecture (ISCA '94, San Diego, CA, May 16-19). ACM Press, New York, NY, 257-266.

Cited By

Radenković UMićović MRadivojević Z(2023)Evaluation and Benefit of Imprecise Value Prediction for Certain Types of InstructionsElectronics10.3390/electronics1217356812:17(3568)Online publication date: 24-Aug-2023
https://doi.org/10.3390/electronics12173568
Pereira EGonçalves G(2023)A Speculative Computing Approach to Accelerate the Task Execution in Cyber-Physical Systems2023 IEEE 9th World Forum on Internet of Things (WF-IoT)10.1109/WF-IoT58464.2023.10539423(1-6)Online publication date: 12-Oct-2023
https://doi.org/10.1109/WF-IoT58464.2023.10539423
Perais A(2021)Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480050(792-803)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480050
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Index Terms

Using value prediction to increase the power of speculative execution hardware
1. Applied computing
  1. Computers in other domains
    1. Personal computers and PC applications
      1. Microcomputers
2. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing

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Information & Contributors

Information

Published In

cover image ACM Transactions on Computer Systems

ACM Transactions on Computer Systems Volume 16, Issue 3

Aug. 1998

112 pages

ISSN:0734-2071

EISSN:1557-7333

DOI:10.1145/290409

Issue’s Table of Contents

Copyright © 1998 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 August 1998

Published in TOCS Volume 16, Issue 3

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Cited By

Radenković UMićović MRadivojević Z(2023)Evaluation and Benefit of Imprecise Value Prediction for Certain Types of InstructionsElectronics10.3390/electronics1217356812:17(3568)Online publication date: 24-Aug-2023
https://doi.org/10.3390/electronics12173568
Pereira EGonçalves G(2023)A Speculative Computing Approach to Accelerate the Task Execution in Cyber-Physical Systems2023 IEEE 9th World Forum on Internet of Things (WF-IoT)10.1109/WF-IoT58464.2023.10539423(1-6)Online publication date: 12-Oct-2023
https://doi.org/10.1109/WF-IoT58464.2023.10539423
Perais A(2021)Leveraging Targeted Value Prediction to Unlock New Hardware Strength Reduction PotentialMICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture10.1145/3466752.3480050(792-803)Online publication date: 18-Oct-2021
https://dl.acm.org/doi/10.1145/3466752.3480050
Kalaitzidis KSeznec A(2020)Leveraging Value Equality Prediction for Value SpeculationACM Transactions on Architecture and Code Optimization10.1145/343682118:1(1-20)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3436821
Parhami B(2019)Tabular ComputationEncyclopedia of Big Data Technologies10.1007/978-3-319-77525-8_169(1667-1672)Online publication date: 20-Feb-2019
https://doi.org/10.1007/978-3-319-77525-8_169
Parhami B(2018)A Case for Table-Based Approximate Computing2018 IEEE 9th Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)10.1109/IEMCON.2018.8614848(650-653)Online publication date: Nov-2018
https://doi.org/10.1109/IEMCON.2018.8614848
Parhami B(2018)Tabular ComputationEncyclopedia of Big Data Technologies10.1007/978-3-319-63962-8_169-1(1-6)Online publication date: 23-Apr-2018
https://doi.org/10.1007/978-3-319-63962-8_169-1
Endo FPerais ASeznec A(2017)On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLEACM Transactions on Architecture and Code Optimization10.1145/309063414:2(1-24)Online publication date: 12-Jul-2017
https://dl.acm.org/doi/10.1145/3090634
Mittal S(2017)A survey of value prediction techniques for leveraging value localityConcurrency and Computation: Practice and Experience10.1002/cpe.425029:21Online publication date: 11-Sep-2017
https://doi.org/10.1002/cpe.4250
Perais AEndo FSeznec AHsu WYang CLipasti MLee H(2016)Register sharing for equality predictionThe 49th Annual IEEE/ACM International Symposium on Microarchitecture10.5555/3195638.3195643(1-12)Online publication date: 15-Oct-2016
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