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- articleJanuary 2011
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture (IJHPSA), Volume 3, Issue 1January 2011, Pages 23–32https://doi.org/10.1504/IJHPSA.2011.038055Current uni-processor centric modelling methodology does not address the new design challenges introduced by MPSoCs, thus, calling for efficient simulation frameworks capable of capturing the interplay between the application, the architecture, and the ...
- articleAugust 2010
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture (IJHPSA), Volume 2, Issue 3/4August 2010, Pages 132–144https://doi.org/10.1504/IJHPSA.2010.034535Computational energy consumption of the processing elements (PEs) of a NoC can be significantly reduced by scaling down their voltage levels. This creates clusters of adjacent PEs operating at the same voltage level, known as voltage islands. Excessive ...
- articleJune 2009
A novel SoC platform based multi-IP verification and performance measurement
International Journal of Information and Communication Technology (IJICT), Volume 2, Issue 1/2June 2009, Pages 120–131https://doi.org/10.1504/IJICT.2009.026435It is well-known that in ASIC designs, verification is more difficult and time consuming than design itself. As the number of IPs in a SoC design increases, IP verification and performance validation have become the important factors in reducing time-to-...
- articleJune 2009
SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration
International Journal of Information and Communication Technology (IJICT), Volume 2, Issue 1/2June 2009, Pages 108–119https://doi.org/10.1504/IJICT.2009.026434The development of digital designs today is much more complex than before, as they now impose more severe demands and require greater number of functionalities to be conceived. The current approach, based on the register transfer level (RTL) design ...
- articleJune 2009
Accelerating the AES encryption function in OpenSSL for embedded systems
International Journal of Information and Communication Technology (IJICT), Volume 2, Issue 1/2June 2009, Pages 83–93https://doi.org/10.1504/IJICT.2009.026432The internet is an insecure medium and hence, there is an increasing demand for measures to guarantee data privacy and integrity in the associated computer systems and networks. However, data protection and network security comes at a very high cost in ...
- articleDecember 2008
Network-on-chip architecture design based on mesh-of-tree deterministic routing topology
International Journal of High Performance Systems Architecture (IJHPSA), Volume 1, Issue 3December 2008, Pages 163–182https://doi.org/10.1504/IJHPSA.2008.021797Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing ...
- articleOctober 2007
Reconfiguration support for vector operations
International Journal of High Performance Systems Architecture (IJHPSA), Volume 1, Issue 2October 2007, Pages 89–97https://doi.org/10.1504/IJHPSA.2007.015394A programmable vector processor and its implementation on a Field-Programmable Gate Array (FPGA) board are presented. This processor is composed of a vector core and a tightly coupled five-stage pipelined RISC scalar unit. It supports the IEEE 754 ...
- articleJune 2006
Developing e-commerce business models for enabling silicon intellectual property transactions
International Journal of Information Technology and Management (IJITM), Volume 5, Issue 2/3June 2006, Pages 114–133https://doi.org/10.1504/IJITM.2006.010113Integrated Circuit (IC) design productivity has failed to keep pace with Moore's Law in the past decade; thus, a 'design productivity gap' between the increase in IC design complexity and increased productivity has emerged. As the IC industry migrates ...
- articleNovember 2005
An IPv6 enabled packet engine design for home/SOHO routers
International Journal of Internet Protocol Technology (IJIPT), Volume 1, Issue 2November 2005, Pages 68–74https://doi.org/10.1504/IJIPT.2005.008041Due to the diversity of internet applications and services, traditional software-based networking devices may not be sufficient to afford the processing load imposed by the services. One example is the mixed-version IP environment in which routers must ...
- articleSeptember 2005
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking (IJHPCN), Volume 3, Issue 1September 2005, Pages 3–18https://doi.org/10.1504/IJHPCN.2005.007862This survey paper identifies some trends in the application, implementation technology, and processor architecture areas. A taxonomy which captures the influence of these trends on processor microsystems is presented, and the communication needs of ...