Computation demands on mobile and edge devices are increasing dramatically. Mobile devices, such as smart phones, incorporate a large number of dedicated accelerators and fixed-function hardware blocks to deliver the required performance and power ...

Multiprocessor Systems-on-Chip (MPSoC) applications can rely today on a very large spectrum of interconnection topologies potentially meeting given communication requirements, determining various trade-offs between cost and performance. Building ...

DIPLODOCUS is a UML profile intended for the modeling and the formal verification of real-time and embedded applications commonly executed on complex Systems-on-Chip. DIPLODOCUS implements the Y-chart approach, that is, application and HW architecture ...

Dependability, availability, reliability and security (in a single word, robustness) are primary-importance elements for today's Systems-on-Chip (SoCs), in different areas. To achieve robustness, functional blocks are combined with fault-detection and ...

The performability metric is commonly used in Networks-on-Chip (NoC)-based systems to represent their abilities to successfully complete specific tasks in finite time intervals. In this paper, we present a novel topology-based performability model for ...

In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in ...

Networks-on-chip (NoCs) have been proposed as a viable solution to solving the communication problem in multicore systems. In this new setup, mapping multiple applications on available computational resources leads to interaction and contention at ...

The roadmap for standardization of electromagnetic (EM) immunity measurement methods has reached a high degree of success with the IEC 62.132 proposal. The same understanding can be taken from the MIL-STD-883H for total ionizing dose (TID) radiation. ...

In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) ...

Networks-on-chip (NoCs) have been proposed as a scalable solution to solving the communication problem in multicore systems. Although the queuing-based approaches have been traditionally used for performance analysis purposes, they cannot properly ...

In order to face the growing complexity of embedded applications, we aim to build highly efficient Network-on-Chip (NoC) architectures which can connect in a scalable manner various computational modules of the platform. For such networked platforms, it ...

Networks-on-Chip (NoCs) are recognized as an interconnection architecture with capability of providing scalable performance, which is an important feature for communication in future SoCs (Systems-on-Chip) with high density. Most NoC models proposed in ...

Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framework for application-aware routing that assures deadlock-freedom under one or ...

Process, voltage, and temperature (PVT) variations are difficult to manage in multi-core SoCs, as each core may have different voltage and reliability requirements. Indeed, common implementations of variation-tolerant techniques (e.g. dynamic voltage ...

The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically ...

This work discusses the adaptation of routers characteristics in Networks-on-Chip to QoS-dependent application requirements, in particular with respect to the fulfillment of task deadlines. The utilization of a flow control mechanism for input buffers ...

The recent shift toward wire pipelining (WP) mandated by technological factors has attracted attention toward latency-controlled floorplanning. However, no systematic study has been published so far that takes into account block and logic-delay ...

When designing a System-on-Chip (SoC) using a Network-on-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power consumption is due to the buffers in the Network Interfaces (NIs) needed ...

Among the many directions of IT, the most pervasive is the fusion of information processing with physical processes - called embedded computing. It is the basic engine of innovation and source of competitiveness for broad range of industrial sectors ...

Complex systems-on-chip are designed by interconnecting pre-designed hardware (HW) and software (SW) components. During the design cycle, a global model of the SoC may be composed of HW and SW models at different abstraction levels. Designing HW/SW ...