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Efficient routing implementation in complex systems-on-chip designs

Published: 01 May 2011 Publication History

Abstract

In application-specific SoCs, the irregularity of the topology ends up in a complex implementation of the routing algorithm, usually relying on routing tables implemented with memory structures. As system size increases, the routing table increases in size with non-negligible impact on power, area and latency overheads. In this paper we present a routing implementation for application-specific SoCs able to implement in an efficient manner (without requiring routing tables and using a small logic block in every switch) a routing algorithm in these irregular networks. The mechanism relies on a tool that maps the initial irregular topology of the SoC system into a logical regular structure where the mechanism can be applied. We provide details on the mapping tool as well the proposed routing mechanism. Evaluation results show the effectiveness of the mapping tool as well as the low area and timing requirements of the mechanism. With the mapping tool and the routing mechanism complex irregular SoC topologies can now be supported without the use of routing tables.

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Cited By

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  • (2018)Semiempirical Model for IC Interconnects Considering the Coupling Between the Signal Trace and the Ground PlaneCircuits, Systems, and Signal Processing10.1007/s00034-017-0742-z37:9(3888-3902)Online publication date: 1-Sep-2018
  • (2015)Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core ArchitecturesACM Transactions on Embedded Computing Systems10.1145/270008114:3(1-25)Online publication date: 21-Apr-2015
  • (2013)Deadlock-Free Fully Adaptive Routing in Irregular Networks without Virtual ChannelsProceedings of the 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2013.120(983-990)Online publication date: 16-Jul-2013
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cover image ACM Conferences
NOCS '11: Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
May 2011
282 pages
ISBN:9781450307208
DOI:10.1145/1999946
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 01 May 2011

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Author Tags

  1. Networks-on-Chip
  2. routing
  3. systems-on-chip

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  • Research-article

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NOCS'11
NOCS'11: International Symposium on Networks-on-Chips
May 1 - 4, 2011
Pennsylvania, Pittsburgh

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Overall Acceptance Rate 14 of 44 submissions, 32%

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Cited By

View all
  • (2018)Semiempirical Model for IC Interconnects Considering the Coupling Between the Signal Trace and the Ground PlaneCircuits, Systems, and Signal Processing10.1007/s00034-017-0742-z37:9(3888-3902)Online publication date: 1-Sep-2018
  • (2015)Modeling and Analyzing Dataflow Applications on NoC-Based Many-Core ArchitecturesACM Transactions on Embedded Computing Systems10.1145/270008114:3(1-25)Online publication date: 21-Apr-2015
  • (2013)Deadlock-Free Fully Adaptive Routing in Irregular Networks without Virtual ChannelsProceedings of the 2013 12th IEEE International Conference on Trust, Security and Privacy in Computing and Communications10.1109/TrustCom.2013.120(983-990)Online publication date: 16-Jul-2013
  • (2012)Transient and Permanent Error Control for High-End Multiprocessor Systems-on-ChipProceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip10.1109/NOCS.2012.27(169-176)Online publication date: 9-May-2012

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