research-article

Application-aware deadlock-free oblivious routing

Authors:

Michel A. Kinsy,

Myong Hyon Cho,

Marten van Dijk,

Srinivas DevadasAuthors Info & Claims

ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture

Pages 208 - 219

https://doi.org/10.1145/1555754.1555782

Published: 20 June 2009 Publication History

Abstract

Conventional oblivious routing algorithms are either not application-aware or assume that each flow has its own private channel to ensure deadlock avoidance. We present a framework for application-aware routing that assures deadlock-freedom under one or more channels by forcing routes to conform to an acyclic channel dependence graph. Arbitrary minimal routes can be made deadlock-free through appropriate static channel allocation when two or more channels are available. Given bandwidth estimates for flows, we present a mixed integer-linear programming (MILP) approach and a heuristic approach for producing deadlock-free routes that minimize maximum channel load. The heuristic algorithm is calibrated using the MILP algorithm and evaluated on a number of benchmarks through detailed network simulation. Our framework can be used to produce application-aware routes that target the minimization of latency, number of flows through a link, bandwidth, or any combination thereof.

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Index Terms

Application-aware deadlock-free oblivious routing
1. Networks
  1. Network protocols

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cover image ACM Conferences

ISCA '09: Proceedings of the 36th annual international symposium on Computer architecture

June 2009

510 pages

ISBN:9781605585260

DOI:10.1145/1555754

General Chair:
Steve Keckler
University of Texas at Austin
,
Program Chair:
Luiz André Barroso
Google Inc.

ACM SIGARCH Computer Architecture News Volume 37, Issue 3
June 2009
495 pages
ISSN:0163-5964
DOI:10.1145/1555815
Issue’s Table of Contents

Copyright © 2009 ACM.

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Published: 20 June 2009

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Cited By

Green CThottethodi M(2024)NetSmith: An Optimization Framework for Machine-Discovered Network TopologiesProceedings of the 53rd International Conference on Parallel Processing10.1145/3673038.3673060(421-432)Online publication date: 12-Aug-2024
https://dl.acm.org/doi/10.1145/3673038.3673060
Mukosey ASemenov ATretiakov A(2023)Graph Based Routing Algorithm for Torus Topology and Its Evaluation for the Angara InterconnectJournal of Parallel and Distributed Computing10.1016/j.jpdc.2023.104765(104765)Online publication date: Sep-2023
https://doi.org/10.1016/j.jpdc.2023.104765
Li YChen L(2020)Accelerated Reply Injection for Removing NoC Bottleneck in GPGPUs2020 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS47924.2020.00013(22-31)Online publication date: May-2020
https://doi.org/10.1109/IPDPS47924.2020.00013
CHU TKISE K(2019)LEF: An Effective Routing Algorithm for Two-Dimensional MeshesIEICE Transactions on Information and Systems10.1587/transinf.2019EDP7019E102.D:10(1925-1941)Online publication date: 1-Oct-2019
https://doi.org/10.1587/transinf.2019EDP7019
Zhang YRucker AVilim MPrabhakar RHwang WOlukotun KManne SHunter HAltman E(2019)Scalable interconnects for reconfigurable spatial architecturesProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322249(615-628)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322249
Pascual JNavaridas J(2018)High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/RoutingsProceedings of the 2018 International Conference on Supercomputing10.1145/3205289.3205307(129-138)Online publication date: 12-Jun-2018
https://dl.acm.org/doi/10.1145/3205289.3205307
Kashi SPatooghy ARahmati DFazeli MKinsy M(2018)Application Specific Networks-on-Chip Synthesis: An Energy Efficient Approach2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI.2018.00020(52-57)Online publication date: Jul-2018
https://doi.org/10.1109/ISVLSI.2018.00020
Jerger NKrishna TPeh L(2017)On-Chip Networks, Second EditionSynthesis Lectures on Computer Architecture10.2200/S00772ED1V01Y201704CAC04012:3(1-210)Online publication date: 17-Jun-2017
https://doi.org/10.2200/S00772ED1V01Y201704CAC040
Doppa JKim RIsakov MKinsy MKwon HKrishna T(2017)Adaptive Manycore Architectures for Big Data ComputingProceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip10.1145/3130218.3130236(1-8)Online publication date: 19-Oct-2017
https://dl.acm.org/doi/10.1145/3130218.3130236
Ramrakhyani AKrishna T(2017)Static Bubble: A Framework for Deadlock-Free Irregular On-chip Topologies2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)10.1109/HPCA.2017.44(253-264)Online publication date: Feb-2017
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